 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| tms320c6413, tms320c6410 fixed-point digital signal processors data manual literature number: sprs247f april 2004 ? revised january 2006
this page intentionally left blank revision history 3 april 2004 ? revised january 2006 sprs247f revision history this data manual revision history highlights the technical changes made to the sprs247e device-specific data manual to make it an sprs247f revision. scope: applicable updates to the c64x device family, specifically relating to the tms320c6413 and tms320c6410 devices, have been incorporated. page(s) no. adds/changes/deletes 13 features, 32?bit external memory interface (emif) section: changed ? 1024 m?byte total addressable memory space? to ? 512 m?byte total addressable memory space? 15 description section: updated ?with performance of up to 3200 million...? paragraph 23 functional overview, memory map summary, tms320c6413/c6410 memory map summary table: updated table 47 device configurations, device configuration at device reset, section: added note 48 device configurations, device configuration at device reset, c6413/c6410 device configuration pins (tout1/lendian, aea[22:19], tout0/hpi_en , hd5, clkinsel, and osc_dis) table: updated aea(22:21) configuration functional description for 11 to ?emifa 8?bit rom boot? 55 device configurations, device status register description, device status (devstat) register selection bit descriptions table: updated bootmode0 and bootmode1 description for 11 to ?emifa 8?bit rom boot? 57 device configurations, debugging considerations section: deleted paragraphs and added note 60 device configurations, terminal functions, terminal functions table, clock/pll configuration section: oscv dd signal name: changed description from ?power for crystal oscillator (1.2 v), do not connect to board power 1.4 v ; ? to ?power for crystal oscillator (1.2 v), do not connect to board power cv dd ; ? 61 device configurations, terminal functions, terminal functions table, resets, interrupts, and general?purpose input/outputs section, nmi signal name: updated description 63 terminal functions table, emifa (32 bit) ? address section: description for aea22 to aea3: added note updated aea(22:3) description for boot mode (aea[21:22]) ? 11 to ?emifa 8?bit rom boot? 91 peripherals detailed description, ieee 1149.1 jtag compatibility statement section: updated paragraphs for clarity 93 device electrical specifications, recommended operating conditions table: updated v os, maximum voltage during overshoot row added v us, minimum voltage during undershoot row 96 parameter measurement information, ac transient rise/fall time specifications section: added ac transient specification rise time figure added ac transient specification fall time figure revision history 4 april 2004 ? revised january 2006 sprs247f page(s) no. adds/changes/deletes 101 peripheral electrical specification, switching characteristics over recommended operating conditions for aeclkout2 for the emifa module table: updated parameter no. 6 from ?t d(eki h -eko2l)? to ?t d(eki l -eko2l)? updated parameter no. 6 from ?delay time, eclkin high to aeclkout2 low? to delay time eclkin low to aeclkout2 low? 101 peripheral electrical specification, aeclkout2 timing for the emifa module figure: updated figure 116 peripheral electrical specifications, reset timing section: added note 121, 122 multichannel audio serial port (mcasp) timing section: updated mcasp input and output drawings contents 5 april 2004 ? revised january 2006 sprs247f contents section page 1 features 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 functional overview 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 gts and zts bga packages (bottom view) 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 description 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 device characteristics 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 functional block diagram 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 cpu (dsp core) description 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 memory map summary 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 l2 architecture expanded 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 peripheral register descriptions 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 edma channel synchronization events 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 interrupt sources and interrupt selector 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 signal groups description 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 device configurations 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 device configuration at device reset 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 peripheral configuration at device reset 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 peripheral selection after device reset 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 peripheral configuration lock 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 device status register description 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 jtag id register description 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 multiplexed pins 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 debugging considerations 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 configuration examples 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 terminal functions 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 development support 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 device support 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 device and development-support tool nomenclature 72 . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 documentation support 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 peripherals detailed description (device-specific) 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 clock pll and oscillator 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 host-port interface (hpi) peripheral 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 multichannel audio serial port (mcasp) peripheral 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 mcasp block diagram 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 i2c 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 general-purpose input/output (gpio) 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 power-down modes logic 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 triggering, wake-up, and effects 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 c64x power-down mode with an emulator 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contents 6 april 2004 ? revised january 2006 sprs247f section page 4.7 power-supply sequencing 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 power-supply design considerations 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 power-supply decoupling 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 peripheral power-down operation 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 ieee 1149.1 jtag compatibility statement 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 emif device speed 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 bootmode 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 reset 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 device electrical specifications 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 absolute maximum ratings over operating case temperature range (unless otherwise noted)? . . 93 5.2 recommended operating conditions 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 electrical characteristics over recommended ranges of supply voltage and operating case tem- perature (unless otherwise noted) 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 recommended clock and control signal transition behavior 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 parameter information 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 signal transition levels 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 signal transition rates 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 ac transient rise/fall time specifications 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 timing parameters and board routing analysis 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 peripheral electrical specifications 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 input and output clocks 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 asynchronous memory timing 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 programmable synchronous interface timing 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 synchronous dram timing 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 hold /holda timing 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 busreq timing 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 reset timing 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 external interrupt timing 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 multichannel audio serial port (mcasp) timing 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 inter-integrated circuits (i2c) timing 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 host-port interface (hpi) timing 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12 multichannel buffered serial port (mcbsp) timing 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.13 timer timing 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.14 general-purpose input/output (gpio) port timing 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.15 jtag test-port timing 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 mechanical data 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 thermal data 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 packaging information 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figures 7 april 2004 ? revised january 2006 sprs247f list of figures figure page 2?1 gts and zts bga packages (bottom view) 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2 functional block diagram 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 tms320c64xe cpu (dsp core) data paths 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 tms320c6413 l2 architecture memory configuration 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 tms320c6410 l2 architecture memory configuration 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6 cpu and peripheral signals 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?7 peripheral signals 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1 peripheral configuration register (percfg) [address location: 0x01b3f000] 50 . . . . . . . . . . . . . . . . . . 3?2 peripheral enable/disable flow diagram 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3 pcfglock register diagram [address location: 0x01b3 f018] ? read/write accesses 53 . . . . . . . . . 3?4 device status register (devstat) description ? 0x01b3 f004 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 jtag id register description ? tms320c6413/c6410 register value ? 0x0007 902f 55 . . . . . . . . . . . . 3?6 configuration example a . . . (hpi16 + 2 mcasps + 2 mcbsps +2 i2cs + emif + 3 timers + gpio) 58 . . . . . . . . . . . . . . . . . . . . . . 3?7 tms320c6413/c6410 dsp device nomenclature 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 external pll circuitry for either pll multiply modes or x1 (bypass) mode 76 . . . . . . . . . . . . . . . . . . . . . . 4?2 mcasp0 and mcasp1 configuration 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?3 i2cx module block diagram 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?4 gpio enable register (gpen) [hex address: 01b0 0000] 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?5 gpio direction register (gpdir) [hex address: 01b0 0004] 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?6 power-down mode logic 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?7 pwrd field of the csr register 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?8 schottky diode diagram 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?1 test load circuit for ac timing measurements 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?2 input and output voltage reference levels for ac timing measurements 95 . . . . . . . . . . . . . . . . . . . . . . 6?3 rise and fall transition time voltage reference levels 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?6 board-level input/output timings 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?1 clkin timing 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?2 clkout4 timing 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?3 clkout6 timing 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?4 aeclkin timing for emifa 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?5 aeclkout1 timing for the emifa module 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?6 aeclkout2 timing for the emifa module 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?7 asynchronous memory read timing for emifa 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?8 asynchronous memory write timing for emifa 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figures 8 april 2004 ? revised january 2006 sprs247f figure page 7?9 programmable synchronous interface read timing for emifa . . . (with read latency = 2) 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?10 programmable synchronous interface write timing for emifa . . (with write latency = 0) 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?11 programmable synchronous interface write timing for emifa . . (with write latency = 1) 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?12 sdram read command (cas latency 3) for emifa 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?13 sdram write command for emifa 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?14 sdram actv command for emifa 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?15 sdram dcab command for emifa 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?16 sdram deac command for emifa 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?17 sdram refr command for emifa 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?18 sdram mrs command for emifa 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?19 sdram self-refresh timing for emifa 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?20 hold /holda timing for emifa 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?21 busreq timing for emifa 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?22 reset timing? 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?23 external/nmi interrupt timing 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?30 i2c receive timings 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?31 i2c transmit timings 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?32 hpi16 read timing (has not used, tied high) 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?33 hpi16 read timing (has used) 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?34 hpi16 write timing (has not used, tied high) 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?35 hpi16 write timing (has used) 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?36 hpi32 read timing (has not used, tied high) 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?37 hpi32 read timing (has used) 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?38 hpi32 write timing (has not used, tied high) 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?39 hpi32 write timing (has used) 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?40 mcbsp timing 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?41 fsr timing when gsync = 1 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?42 mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 133 . . . . . . . . . . . . . . . . . . . . . . . . . . 7?43 mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 134 . . . . . . . . . . . . . . . . . . . . . . . . . . 7?44 mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 135 . . . . . . . . . . . . . . . . . . . . . . . . . . 7?45 mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 136 . . . . . . . . . . . . . . . . . . . . . . . . . . 7?46 timer timing 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?47 gpio port timing 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?48 jtag test-port timing 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tables 9 april 2004 ? revised january 2006 sprs247f list of tables table page 2?1 characteristics of the c6413 and c6410 processors 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2 tms320c6413/c6410 memory map summary 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 emifa registers 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 l2 cache registers (c64x) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 quick dma (qdma) and pseudo registers 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6 edma registers (c64x) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?7 edma parameter ram (c64x) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?8 interrupt selector registers (c64x) 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?9 device configuration registers 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?10 mcbsp 0 registers 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?11 mcbsp 1 registers 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?12 timer 0 registers 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?13 timer 1 registers 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 timer 2 registers 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?15 hpi registers 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?16 gp0 registers 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?17 mcasp0 and mcasp1 control registers 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?18 mcasp0 data registers 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?19 mcasp1 data registers 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?20 i2c0 and i2c1 registers 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?21 tms320c6413/c6410 edma channel synchronization events 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?22 c6413/c6410 dsp interrupts 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1 c6413/c6410 device configuration pins (tout1/lendian, aea[22:19], tout0/hpi_en, . . . hd5, clkinsel, and osc_dis) 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?2 tout0/hpi_en and hd5 peripheral selection (hpi or mcasp1 and select gp0 pins) 49 . . . . . . . . . . 3?3 peripheral configuration (percfg) register selection bit descriptions 51 . . . . . . . . . . . . . . . . . . . . . . . 3?4 pcfglock register selection bit descriptions ? read accesses 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 pcfglock register selection bit descriptions ? write accesses 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?6 device status (devstat) register selection bit descriptions 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?7 jtag id register selection bit descriptions 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?8 c6413/c6410 device multiplexed pins 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?9 terminal functions 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 tms320c6413 pll multiply factor options, clock frequency ranges, and typical lock time for . . . ?500 devices 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?2 tms320c6410 pll multiply factor options, clock frequency ranges, and typical lock time for . . . ?400 devices 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?3 crystal and tank circuit recommendations 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?4 characteristics of the power-down modes 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?1 board-level timing example 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?1 timing requirements for external crystal oscillator input (oscin and oscout) 98 . . . . . . . . . . . . . . . tables 10 april 2004 ? revised january 2006 sprs247f 7?2 timing requirements for clkin 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?3 switching characteristics over recommended operating conditions for clkout4 99 . . . . . . . . . . . . . 7?4 switching characteristics over recommended operating conditions for clkout6 99 . . . . . . . . . . . . . 7?5 timing requirements for aeclkin for emifa 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?6 switching characteristics over recommended operating conditions for aeclkout1 for the emifa . . . module 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?7 switching characteristics over recommended operating conditions for aeclkout2 for . . . the emifa module 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?8 timing requirements for asynchronous memory cycles for emifa module 102 . . . . . . . . . . . . . . . . . . . . . 7?9 switching characteristics over recommended operating conditions for asynchronous memory . . . cycles for emifa module 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?10 timing requirements for programmable synchronous interface cycles for emifa module 105 . . . . . . 7?11 switching characteristics over recommended operating conditions for programmable . . synchronous interface cycles for emifa module 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?12 timing requirements for synchronous dram cycles for emifa module 109 . . . . . . . . . . . . . . . . . . . . . . 7?13 switching characteristics over recommended operating conditions for synchronous dram . . cycles for emifa module 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?14 timing requirements for the hold /holda cycles for emifa module 115 . . . . . . . . . . . . . . . . . . . . . . . . 7?15 switching characteristics over recommended operating conditions for the hold /holda . . cycles for emifa module 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?16 switching characteristics over recommended operating conditions for the busreq cycles . . for emifa module 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?17 timing requirements for reset 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?18 switching characteristics over recommended operating conditions during reset 117 . . . . . . . . . . . . . 7?19 timing requirements for external interrupts 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?20 timing requirements for mcasp 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?21 switching characteristics over recommended operating conditions for mcasp 120 . . . . . . . . . . . . . . . 7?22 timing requirements for i2c timings 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?23 switching characteristics for i2c timings 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?24 timing requirements for host-port interface cycles 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?25 switching characteristics over recommended operating conditions during host-port . . interface cycles 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?26 timing requirements for mcbsp 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?27 switching characteristics over recommended operating conditions for mcbsp 131 . . . . . . . . . . . . . . . 7?28 timing requirements for fsr when gsync = 1 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?29 timing requirements for mcbsp as spi master or slave: . . clkstp = 10b, clkxp = 0 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?30 switching characteristics over recommended operating conditions for mcbsp as . . spi master or slave: clkstp = 10b, clkxp = 0 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?31 timing requirements for mcbsp as spi master or slave: . . clkstp = 11b, clkxp = 0 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?32 switching characteristics over recommended operating conditions for mcbsp as . . spi master or slave: clkstp = 11b, clkxp = 0 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?33 timing requirements for mcbsp as spi master or slave: . . clkstp = 10b, clkxp = 1 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?34 switching characteristics over recommended operating conditions for mcbsp as . . spi master or slave: clkstp = 10b, clkxp = 1 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?35 timing requirements for mcbsp as spi master or slave: . . clkstp = 11b, clkxp = 1 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?36 switching characteristics over recommended operating conditions for mcbsp as . . spi master or slave: clkstp = 11b, clkxp = 1 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?37 timing requirements for timer inputs 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?38 switching characteristics over recommended operating conditions for timer outputs 137 . . . . . . . . . tables 11 april 2004 ? revised january 2006 sprs247f 7?39 timing requirements for gpio inputs 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?40 switching characteristics over recommended operating conditions for gpio outputs 138 . . . . . . . . . 7?41 timing requirements for jtag test port 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?42 switching characteristics over recommended operating conditions for jtag test port 139 . . . . . . . . 8?1 thermal resistance characteristics (s-pbga package) [gts] 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8?2 thermal resistance characteristics (s-pbga package) [zts] 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tables 12 april 2004 ? revised january 2006 sprs247f this page intentionally left blank features 13 april 2004 ? revised january 2006 sprs247f 1 features high-performance fixed-point digital signal processor (tms320c6413/c6410) ? tms320c6413 ? 2-ns instruction cycle time ? 500-mhz clock rate ? 4000 mips ? tms320c6410 ? 2.5-ns instruction cycle time ? 400-mhz clock rate ? 3200 mips ? eight 32-bit instructions/cycle ? fully software-compatible with c64x ? ? extended temperature devices available velociti.2 ? extensions to velociti ? advanced very-long-instruction-word (vliw) tms320c64x ? dsp core ? eight highly independent functional units with velociti.2 ? extensions: ? six alus (32-/40-bit), each supports single 32-bit, dual 16-bit, or quad 8-bit arithmetic per clock cycle ? two multipliers support four 16 x 16-bit multiplies (32-bit results) per clock cycle or eight 8 x 8-bit multiplies (16-bit results) per clock cycle ? load-store architecture with non-aligned support ? 64 32-bit general-purpose registers ? instruction packing reduces code size ? all instructions conditional instruction set features ? byte-addressable (8-/16-/32-/64-bit data) ? 8-bit overflow protection ? bit-field extract, set, clear ? normalization, saturation, bit-counting ? velociti.2 ? increased orthogonality velociti.2 ? extensions to velociti ? advanced very-long-instruction-word (vliw) tms320c64x ? dsp core l1/l2 memory architecture ? 128k-bit (16k-byte) l1p program cache (direct mapped) ? 128k-bit (16k-byte) l1d data cache (2-way set-associative) ? 2m-bit (256k-byte) l2 unified mapped ram/cache [c6413] (flexible ram/cache allocation) ? 1m-bit (128k-byte) l2 unified mapped ram/cache [c6410] (flexible ram/cache allocation) endianess: little endian, big endian 32-bit external memory interface (emif) ? glueless interface to asynchronous memories (sram and eprom) and synchronous memories (sdram, sbsram, zbt sram, and fifo) ? 512m-byte total addressable external memory space enhanced direct-memory-access (edma) controller (64 independent channels) host-port interface (hpi) [32-/16-bit] two multichannel audio serial ports (mcasps) - with six serial data pins each two inter-integrated circuit (i 2 c) buses ? additional gpio capability two multichannel buffered serial ports three 32-bit general-purpose timers sixteen general-purpose i/o (gpio) pins flexible pll clock generator on-chip fundamental oscillator ieee-1149.1 (jtag ? ) boundary-scan-compatible 288-pin ball grid array (bga) packages (gts and zts suffixes), 1.0-mm ball pitch 0.13- m/6-level cu metal process (cmos) 3.3-v i/os, 1.2-v internal velociti.2, velociti, and tms320c64x are trademarks of texas instruments. all trademarks are the property of their respective owners. ? ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture. functional overview 14 april 2004 ? revised january 2006 sprs247f 2 functional overview 2.1 gts and zts bga packages (bottom view) gts and zts 288-pin ball grid array (bga) packages ( bottom view ) ab aa y w v u t r p n m l k j h g f e d c 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 b 2 a figure 2?1. gts and zts bga packages (bottom view) description 15 april 2004 ? revised january 2006 sprs247f 2.2 description the tms320c64x ? dsps (including the tms320c6413, tms320c6410 devices) are the highest-performance fixed-point dsp generation in the tms320c6000 ? dsp platform. the tms320c6413 and tms320c6410 (c6413 and c6410) devices are based on the second-generation high-performance, advanced velociti ? very-long-instruction-word (vliw) architecture (velociti.2 ? ) developed by texas instruments (ti). the high-performance, lower-cost c6413/c6410 dsps enable customers to reduce system costs for telecom, medical, industrial, office, and photo lab equipment. the c64x ? is a code-compatible member of the c6000 ? dsp platform. with performance of up to 4000 million instructions per second (mips) at a clock rate of 500 mhz, the c6413 device offers cost-effective solutions to high-performance dsp programming challenges. with performance of up to 3200 million instructions per second (mips) at a clock rate of 400 mhz, the c6410 device offers cost-effective solutions to high-performance dsp programming challenges. the c6410 device also provides excellent value for packet telephony and for other cost?sensitive applications demanding high performance. the c6410 device also provides excellent value for packet telephony and to other cost?sensitive applications demanding high performance the c6413/c6410 dsp possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. the c64x ? dsp core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units?two multipliers for a 32-bit result and six arithmetic logic units (alus)? with velociti.2 ? extensions. the velociti.2 ? extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the velociti ? architecture. the c6413 can produce four 16-bit multiply-accumulates (macs) per cycle for a total of 2000 million macs per second (mmacs), or eight 8-bit macs per cycle for a total of 4000 mmacs. the c6410 can produce four 16-bit multiply-accumulates (macs) per cycle for a total of 1600 million macs per second (mmacs), or eight 8-bit macs per cycle for a total of 3200 mmacs. the c6413/c6410 dsp also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other c6000 ? dsp platform devices. the c6413/c6410 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. the level 1 program cache (l1p) is a 128-kbit direct mapped cache and the level 1 data cache (l1d) is a 128-kbit 2-way set-associative cache. the level 2 memory/cache (l2) consists of an 2-mbit memory space that is shared between program and data space [for c6413 device] and the level 2 memory/cache (l2) consists of an 1-mbit memory space that is shared between program and data space [for c6410 device]. l2 memory can be configured as mapped memory, cache, or combinations of the two. the peripheral set includes: two multichannel buffered audio serial ports (mcasps); two inter-integrated circuit bus modules (i2cs) ; two multichannel buffered serial ports (mcbsps); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (hpi16/hpi32); a 16-pin general-purpose input/output port (gp0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (emifa), which is capable of interfacing to synchronous and asynchronous memories and peripherals. each mcasp port supports one transmit and one receive clock zone, with six serial data pins which can be individually allocated to any of the two zones. the serial port supports time-division multiplexing on each pin from 2 to 32 time slots. the c6413/c6410 has sufficient bandwidth to support all six serial data pins transmitting a 192-khz stereo signal. serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the philips inter-ic sound (i 2 s) format. in addition, the mcasp transmitter may be programmed to output multiple s/pdif, iec60958, aes-3, cp-430 encoded data channels simultaneously, with a single ram containing the full implementation of user data and channel status fields. tms320c6000, and c6000 are trademarks of texas instruments. description 16 april 2004 ? revised january 2006 sprs247f mcasp also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range . the i2c ports on the tms320c6413/c6410 allows the dsp to easily control peripheral devices and communicate with a host processor. in addition, the standard multichannel buffered serial port (mcbsp) may be used to communicate with serial peripheral interface (spi) mode peripheral devices. the c6413/c6410 has a complete set of development tools which includes: a new c compiler, an assembly optimizer to simplify programming and scheduling, and a windows ? debugger interface for visibility into source code execution. device characteristics 17 april 2004 ? revised january 2006 sprs247f 2.3 device characteristics table 2?1, provides an overview of the c6413 and c6410 dsps. the tables show significant features of the c6413 and c6410 devices, including the capacity of on-chip ram, the peripherals, the cpu frequency, and the package type with pin count. table 2?1. characteristics of the c6413 and c6410 processors hardware features c6413 and c6410 emifa (32-bit bus width) (clock source = aeclkin, clkout4, or clkout6) 1 peripherals edma (64 independent channels) 1 peripherals mcasps (use peripheral clock and auxclk) 2 not all peripherals pins i2cs (use peripheral clock) 2 not all peripherals pins are available at the same time (for more hpi (32- or 16-bit user selectable) 1 (hpi16 or hpi32) are available at the same time (for more detail, see the device configuration section). mcbsps (internal clock source = cpu/4 clock frequency) 2 configuration section). 32-bit timers (internal clock source = cpu/8 clock frequency) 3 general-purpose input/output port (gp0) 16 size (bytes) 288k ( c6413 ) 160k ( c6410 ) on-chip memory organization 16k-byte (16kb) l1 program (l1p) cache 16kb l1 data (l1d) cache 256kb unified mapped ram/cache (l2) [ c6413 ] 128kb unified mapped ram/cache (l2) [ c6410 ] cpu id + cpu rev id control status register (csr.[31:16]) 0x0c01 jtag bsdl_id jtagid register (address location: 0x01b3f008) 0x0007902f frequency mhz 500 ( c6413 ) 400 ( c6410 ) cycle time ns 2 ns ( c6413-500, c6413 a?500 ) [500 mhz cpu, 100 mhz emif ? ] 2.5 ns ( c6410-400, c6410 a?400 ) [400 mhz cpu, 100 mhz emif ? ] voltage core (v) 1.2 v voltage i/o (v) 3.3 v pll options clkin frequency multiplier bypass (x1), x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, and x24 bga package 23 x 23 mm 288-pin flip-chip plastic bga (gts and zts) process technology m 0.13 m product status ? product preview (pp), advance information (ai), or production data (pd) pd ? on this c64x ? device, the rated emif speed affects only the sdram interface on the emif. for more detailed information, see the emif device speed portion of this data sheet. ? production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. functional block diagram 18 april 2004 ? revised january 2006 sprs247f 2.3.1 functional block diagram figure 2?2 shows the functional block diagram of the c6413/c6410 device. test c64x dsp core data path b b register file b31?b16 b15?b0 instruction fetch instruction dispatch advanced instruction packet instruction decode data path a a register file a31?a16 a15?a0 power-down logic .l1 .s1 .m1 .d1 .d2 .m2 .s2 .l2 32 sdram fifo sbsram sram l1p cache direct-mapped 16k bytes total control registers control logic l1d cache 2-way set-associative 16k bytes total advanced in-circuit emulation interrupt control tms320c6413/c6410 enhanced dma controller (edma) l2 cache memory 256kbytes oscillator and pll (x1, x5 ? x12, x16, x18, x19 ? x22, x24) timer 2 emif a zbt sram timer 1 boot configuration rom/flash i/o devices mcbsp0 gp0 16 timer 0 mcbsp1 mcasp0 gp0 ? 16 and or hpi32 hpi16 mcasp1 ? mcbsps: framing chips ? h.100, mvip, scsa, t1, e1; ac97 devices; spi devices; codecs ? gp0[15:8] pins are muxed with the hpi hd[15:8] pins and gp0[2:1] pins are muxed with clkout6 and clkout4, respectively. note: the c6413 device has 256k-bytes l2 cache memory; the c6410 device has only 128k-bytes l2 cache memory. i2c0 i2c1 figure 2?2. functional block diagram cpu (dsp core) description 19 april 2004 ? revised january 2006 sprs247f 2.4 cpu (dsp core) description the cpu fetches velociti ? advanced very-long instruction words (vliws) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units dur ing every cloc k cycle. the v elociti ? vliw architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. the first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. fetch packets are always 256 bits wide; however, the execute packets can vary in size. the variable-length execute packets are a key memory-saving feature, distinguishing the c64x cpus from other vliw architectures. the c64x ? velociti.2 ? extensions add enhancements to the tms320c62x ? dsp velociti ? architecture. these enhancements include: ? register file enhancements ? data path extensions ? quad 8-bit and dual 16-bit extensions with data flow enhancements ? additional functional unit hardware ? increased orthogonality of the instruction set ? additional instructions that reduce code size and increase register flexibility the cpu features two sets of functional units. each set contains four units and a register file. one set contains functional units .l1, .s1, .m1, and .d1; the other set contains units .d2, .m2, .s2, and .l2. the two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. in addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the c62x ? velociti ? vliw architecture, the c64x ? register files also support packed 8-bit data and 64-bit fixed-point data types. the two sets of functional units, along with two register files, compose sides a and b of the cpu [see the functional block and cpu (dsp core) diagram, and figure 2?3]. the four functional units on each side of the cpu can freely share the 32 registers belonging to that side. additionally, each side features a ?data cross path??a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. the c64x cpu pipelines data-cross-path accesses over multiple clock cycles. this allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. all functional units in the c64x cpu can access operands via the data cross path. register access by functional units on the same side of the cpu as the register file can service all the units in a single clock cycle. on the c64x cpu, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. in addition to the c62x ? dsp fixed-point instructions, the c64x ? dsp includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. these velociti.2 ? extensions allow the c64x cpu to operate directly on packed data to streamline data flow and increase instruction set efficiency. another key feature of the c64x cpu is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). two sets of data-addressing units (.d1 and .d2) are responsible for all data transfers between the register files and the memory. the data address driven by the .d units allows data addresses generated from one register file to be used to load or store data to or from the other register file. the c64x .d units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. and with the new data path extensions, the c64x .d unit can load and store doublewords (64 bits) with a single instruction. furthermore, the non-aligned load and s tore instructions allow the .d units to access words and doublewords on any byte boundary. the c64x cpu supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. all instructions are conditional, and most can access any one of the 64 registers. some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically ?true?). tms320c62x and c62x are trademarks of texas instruments. cpu (dsp core) description 20 april 2004 ? revised january 2006 sprs247f the two .m functional units perform all multiplication operations. each of the c64x .m units can perform two 16 16-bit multiplies or four 8 8-bit multiplies per clock cycle. the .m unit can also perform 16 32-bit multiply operations, dual 16 16-bit multiplies with add/subtract operations, and quad 8 8-bit multiplies with add operations. in addition to standard multiplies, the c64x .m units include bit-count, rotate, galois field multiplies, and bidirectional variable shift hardware. the two .s and .l functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. the arithmetic and logical functions on the c64x cpu include single 32-bit, dual 16-bit, and quad 8-bit operations. the processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. the 32-bit instructions destined for the individual functional units are ?linked? together by ?1? bits in the least significant bit (lsb) position of the instructions. the instructions that are ?chained? together for simultaneous execution (up to eight in total) compose an execute packet. a ?0? in the lsb of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. a c64x ? dsp device enhancement now allows execute packets to cross fetch-packet boundaries. in the tms320c62x ? /tms320c67x ? dsp devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with nop instructions. in the c64x ? dsp device, the execute boundary restrictions have been removed, thereby, eliminating all of the nops added to pad the fetch packet, and thus, decreasing the overall code size. the number of execute packets within a fetch packet can vary from one to eight. execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. after decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. while most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, or doublewords. all load and store instructions are byte-, half-word-, word-, or doubleword-addressable. for more details on the c64x cpu functional units enhancements, see the following documents: ? tms320c6000 cpu and instruction set reference guide (literature number spru189) ? tms320c64x technical overview (literature number spru395) tms320c67x is a trademark of texas instruments. cpu (dsp core) description 21 april 2004 ? revised january 2006 sprs247f .l1 .s1 .m1 .d1 .d2 .m2 .s2 .l2 src1 long dst 8 8 src2 da1 (address) st1b (store data) st2a (store data) register file a (a0?a31) 8 8 8 8 dst data path a da2 (address) register file b (b0? b31) ld2a (load data) data path b control register file st2b (store data) ld1b (load data) 8 8 2x 1x st1a (store data) see note a see note a ld1a (load data) ld2b (load data) see note a see note a 32 msbs 32 lsbs 32 msbs 32 lsbs 32 msbs 32 lsbs 32 msbs 32 lsbs src2 src1 dst long dst long src long src long dst dst src1 src2 src1 src2 src2 src1 dst src2 src1 dst src2 long dst src2 src1 dst long dst long dst long src long src long dst dst dst src2 src1 dst note a: for the .m functional units, the long dst is 32 msbs and the dst is 32 lsbs. figure 2?3. tms320c64x ? cpu (dsp core) data paths memory map summary 22 april 2004 ? revised january 2006 sprs247f 2.5 memory map summary table 2?2 shows the memory map address ranges of the c6413 and c6410 devices. internal memory is always located at address 0 and can be used as both program and data memory. the external memory address ranges in the c6413/c6410 device begin at the hex address location 0x8000 0000 for emifa. table 2?2. tms320c6413/c6410 memory map summary memory block description block size (bytes) hex address range internal ram (l2) [c6413] 256k 0000 0000 ? 0003 ffff reserved [c6413] 1024k minus 256k 0004 0000 ? 000f ffff internal ram (l2) [c6410] 128k 0000 0000 ? 0001 ffff reserved [c6410] 1024k minus 128k 0002 0000 ? 000f ffff reserved 15m 0010 0000 ? 00ff ffff reserved 8m 0100 0000 ? 017f ffff external memory interface a (emifa) registers 256k 0180 0000 ? 0183 ffff l2 registers 256k 0184 0000 ? 0187 ffff hpi registers 256k 0188 0000 ? 018b ffff mcbsp 0 registers 256k 018c 0000 ? 018f ffff mcbsp 1 registers 256k 0190 0000 ? 0193 ffff timer 0 registers 256k 0194 0000 ? 0197 ffff timer 1 registers 256k 0198 0000 ? 019b ffff interrupt selector registers 256k 019c 0000 ? 019f ffff edma ram and edma registers 256k 01a0 0000 ? 01a3 ffff reserved 512k 01a4 0000 ? 01ab ffff timer 2 registers 256k 01ac 0000 ? 01af ffff gp0 registers 256k minus 4k 01b0 0000 ? 01b3 efff device configuration registers 4k 01b3 f000 ? 01b3 ffff i2c0 data and control registers 16k 01b4 0000 ? 01b4 3fff i2c1 data and control registers 16k 01b4 4000 ? 01b4 7fff reserved 16k 01b4 8000 ? 01b4 bfff mcasp0 control registers 16k 01b4 c000 ? 01b4 ffff mcasp1 control registers 16k 01b5 0000 ? 01b5 3fff reserved 176k 01b5 4000 ? 01b7 ffff reserved 128k 01b8 0000 ? 01b9 ffff reserved 128k 01ba 0000 ? 01bb ffff emulation 256k 01bc 0000 ? 01bf ffff reserved 528k 01c0 0000 ? 01c8 3fff reserved 3.5m 01c8 4000 ? 01ff ffff qdma registers 52 0200 0000 ? 0200 0033 reserved 928m minus 52 0200 0034 ? 2fff ffff mcbsp 0 data 64m 3000 0000 ? 33ff ffff mcbsp 1 data 64m 3400 0000 ? 37ff ffff reserved 64m 3800 0000 ? 3bff ffff mcasp0 data 1m 3c00 0000 ? 3c0f ffff memory map summary 23 april 2004 ? revised january 2006 sprs247f table 2?2. tms320c6413/c6410 memory map summary (continued) memory block description hex address range block size (bytes) mcasp1 data 1m 3c10 0000 ? 3c1f ffff reserved 62m 3c20 0000 ? 3fff ffff reserved 1g 4000 0000 ? 7fff ffff emifa ce0 128m 8000 0000 ? 87ff ffff reserved 128m 8800 0000 ? 8fff ffff emifa ce1 128m 9000 0000 ? 97ff ffff reserved 128m 9800 0000 ? 9fff ffff emifa ce2 128m a000 0000 ? a7ff ffff reserved 128m a800 0000 ? afff ffff emifa ce3 128m b000 0000 ? b7ff ffff reserved 128m b800 0000 ? bfff ffff reserved 1g c000 0000 ? ffff ffff memory map summary 24 april 2004 ? revised january 2006 sprs247f 2.5.1 l2 architecture expanded figure 2?4 and figure 2?5 show the detail of the l2 architecture on the tms320c6413 and tms320c6410 devices, respectively . for more information on the l2mode bits, see the cache configuration (ccfg) register bit field descriptions in the tms320c64x two-level internal memory reference guide (literature number spru610). ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? 0x0000 0000 011 010 001 111 0x0002 0000 000 l2mode l2 memory block base address 0x0003 8000 0x0003 0000 0x0004 0000 32k cache (4 way) 64k cache (4 way) 128k cache (4 way) 256k cache (4 way) [all] 256k sram (all) 224k sram 192k sram 128k sram 128k-byte sram 64k-byte ram 32k-byte ram 0x0003 ffff 32k-byte ram figure 2?4. tms320c6413 l2 architecture memory configuration memory map summary 25 april 2004 ? revised january 2006 sprs247f ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? 011 010 001 0x0000 0000 000 l2 memory block base address 0x0001 8000 0x0001 0000 0x0002 0000 32k cache (4 way) 64k cache (4 way) 128k cache (4 way) 128k sram (all) 96k sram 64k sram 64k-byte ram 32k-byte ram 0x0001 ffff 32k-byte ram ? the l2mode = 111b is not supported on the c6410 device. l2mode ? figure 2?5. tms320c6410 l2 architecture memory configuration peripheral register descriptions 26 april 2004 ? revised january 2006 sprs247f 2.6 peripheral register descriptions table 2?3 through table 2?20 identify the peripheral registers for the c6413/c6410 device by their register names, acronyms, and hex address or hex address range. for more detailed information on the register contents, bit names and their descriptions, see the specific peripheral reference guide listed in the tms320c6000 dsp peripherals overview reference guide (literature number spru190). table 2?3. emifa registers hex address range acronym register name comments 0180 0000 gblctl emifa global control 0180 0004 cectl1 emifa ce1 space control 0180 0008 cectl0 emifa ce0 space control 0180 000c ? reserved 0180 0010 cectl2 emifa ce2 space control 0180 0014 cectl3 emifa ce3 space control 0180 0018 sdctl emifa sdram control 0180 001c sdtim emifa sdram refresh control 0180 0020 sdext emifa sdram extension 0180 0024 ? 0180 003c ? reserved 0180 0040 pdtctl peripheral device transfer (pdt) control 0180 0044 cesec1 emifa ce1 space secondary control 0180 0048 cesec0 emifa ce0 space secondary control 0180 004c ? reserved 0180 0050 cesec2 emifa ce2 space secondary control 0180 0054 cesec3 emifa ce3 space secondary control 0180 0058 ? 0183 ffff ? reserved table 2?4. l2 cache registers (c64x) hex address range acronym register name comments 0184 0000 ccfg cache configuration register 0184 0004 ? 0184 0ffc ? reserved 0184 1000 edmaweight l2 edma access control register 0184 1004 ? 0184 1ffc ? reserved 0184 2000 l2alloc0 l2 allocation register 0 0184 2004 l2alloc1 l2 allocation register 1 0184 2008 l2alloc2 l2 allocation register 2 0184 200c l2alloc3 l2 allocation register 3 0184 2010 ? 0184 3ffc ? reserved 0184 4000 l2wbar l2 writeback base address register 0184 4004 l2wwc l2 writeback word count register 0184 4010 l2wibar l2 writeback invalidate base address register 0184 4014 l2wiwc l2 writeback invalidate word count register 0184 4018 l2ibar l2 invalidate base address register 0184 401c l2iwc l2 invalidate word count register 0184 4020 l1pibar l1p invalidate base address register 0184 4024 l1piwc l1p invalidate word count register 0184 4030 l1dwibar l1d writeback invalidate base address register peripheral register descriptions 27 april 2004 ? revised january 2006 sprs247f table 2?4. l2 cache registers (c64x) (continued) hex address range comments register name acronym 0184 4034 l1dwiwc l1d writeback invalidate word count register 0184 4038 ? 0184 4044 ? reserved 0184 4048 l1dibar l1d invalidate base address register 0184 404c l1diwc l1d invalidate word count register 0184 4050 ? 0184 4ffc ? reserved 0184 5000 l2wb l2 writeback all register 0184 5004 l2wbinv l2 writeback invalidate all register 0184 5008 ? 0184 7ffc ? reserved 0184 8000 ? 0184 81fc mar0 to mar127 reserved 0184 8200 mar128 controls emifa ce0 range 8000 0000 ? 80ff ffff 0184 8204 mar129 controls emifa ce0 range 8100 0000 ? 81ff ffff 0184 8208 mar130 controls emifa ce0 range 8200 0000 ? 82ff ffff 0184 820c mar131 controls emifa ce0 range 8300 0000 ? 83ff ffff 0184 8210 mar132 controls emifa ce0 range 8400 0000 ? 84ff ffff 0184 8214 mar133 controls emifa ce0 range 8500 0000 ? 85ff ffff 0184 8218 mar134 controls emifa ce0 range 8600 0000 ? 86ff ffff 0184 821c mar135 controls emifa ce0 range 8700 0000 ? 87ff ffff 0184 8220 mar136 controls emifa ce0 range 8800 0000 ? 88ff ffff 0184 8224 mar137 controls emifa ce0 range 8900 0000 ? 89ff ffff 0184 8228 mar138 controls emifa ce0 range 8a00 0000 ? 8aff ffff 0184 822c mar139 controls emifa ce0 range 8b00 0000 ? 8bff ffff 0184 8230 mar140 controls emifa ce0 range 8c00 0000 ? 8cff ffff 0184 8234 mar141 controls emifa ce0 range 8d00 0000 ? 8dff ffff 0184 8238 mar142 controls emifa ce0 range 8e00 0000 ? 8eff ffff 0184 823c mar143 controls emifa ce0 range 8f00 0000 ? 8fff ffff 0184 8240 mar144 controls emifa ce1 range 9000 0000 ? 90ff ffff 0184 8244 mar145 controls emifa ce1 range 9100 0000 ? 91ff ffff 0184 8248 mar146 controls emifa ce1 range 9200 0000 ? 92ff ffff 0184 824c mar147 controls emifa ce1 range 9300 0000 ? 93ff ffff 0184 8250 mar148 controls emifa ce1 range 9400 0000 ? 94ff ffff 0184 8254 mar149 controls emifa ce1 range 9500 0000 ? 95ff ffff 0184 8258 mar150 controls emifa ce1 range 9600 0000 ? 96ff ffff 0184 825c mar151 controls emifa ce1 range 9700 0000 ? 97ff ffff 0184 8260 mar152 controls emifa ce1 range 9800 0000 ? 98ff ffff 0184 8264 mar153 controls emifa ce1 range 9900 0000 ? 99ff ffff 0184 8268 mar154 controls emifa ce1 range 9a00 0000 ? 9aff ffff 0184 826c mar155 controls emifa ce1 range 9b00 0000 ? 9bff ffff 0184 8270 mar156 controls emifa ce1 range 9c00 0000 ? 9cff ffff 0184 8274 mar157 controls emifa ce1 range 9d00 0000 ? 9dff ffff 0184 8278 mar158 controls emifa ce1 range 9e00 0000 ? 9eff ffff 0184 827c mar159 controls emifa ce1 range 9f00 0000 ? 9fff ffff 0184 8280 mar160 controls emifa ce2 range a000 0000 ? a0ff ffff peripheral register descriptions 28 april 2004 ? revised january 2006 sprs247f table 2?4. l2 cache registers (c64x) (continued) hex address range comments register name acronym 0184 8284 mar161 controls emifa ce2 range a100 0000 ? a1ff ffff 0184 8288 mar162 controls emifa ce2 range a200 0000 ? a2ff ffff 0184 828c mar163 controls emifa ce2 range a300 0000 ? a3ff ffff 0184 8290 mar164 controls emifa ce2 range a400 0000 ? a4ff ffff 0184 8294 mar165 controls emifa ce2 range a500 0000 ? a5ff ffff 0184 8298 mar166 controls emifa ce2 range a600 0000 ? a6ff ffff 0184 829c mar167 controls emifa ce2 range a700 0000 ? a7ff ffff 0184 82a0 mar168 controls emifa ce2 range a800 0000 ? a8ff ffff 0184 82a4 mar169 controls emifa ce2 range a900 0000 ? a9ff ffff 0184 82a8 mar170 controls emifa ce2 range aa00 0000 ? aaff ffff 0184 82ac mar171 controls emifa ce2 range ab00 0000 ? abff ffff 0184 82b0 mar172 controls emifa ce2 range ac00 0000 ? acff ffff 0184 82b4 mar173 controls emifa ce2 range ad00 0000 ? adff ffff 0184 82b8 mar174 controls emifa ce2 range ae00 0000 ? aeff ffff 0184 82bc mar175 controls emifa ce2 range af00 0000 ? afff ffff 0184 82c0 mar176 controls emifa ce3 range b000 0000 ? b0ff ffff 0184 82c4 mar177 controls emifa ce3 range b100 0000 ? b1ff ffff 0184 82c8 mar178 controls emifa ce3 range b200 0000 ? b2ff ffff 0184 82cc mar179 controls emifa ce3 range b300 0000 ? b3ff ffff 0184 82d0 mar180 controls emifa ce3 range b400 0000 ? b4ff ffff 0184 82d4 mar181 controls emifa ce3 range b500 0000 ? b5ff ffff 0184 82d8 mar182 controls emifa ce3 range b600 0000 ? b6ff ffff 0184 82dc mar183 controls emifa ce3 range b700 0000 ? b7ff ffff 0184 82e0 mar184 controls emifa ce3 range b800 0000 ? b8ff ffff 0184 82e4 mar185 controls emifa ce3 range b900 0000 ? b9ff ffff 0184 82e8 mar186 controls emifa ce3 range ba00 0000 ? baff ffff 0184 82ec mar187 controls emifa ce3 range bb00 0000 ? bbff ffff 0184 82f0 mar188 controls emifa ce3 range bc00 0000 ? bcff ffff 0184 82f4 mar189 controls emifa ce3 range bd00 0000 ? bdff ffff 0184 82f8 mar190 controls emifa ce3 range be00 0000 ? beff ffff 0184 82fc mar191 controls emifa ce3 range bf00 0000 ? bfff ffff 0184 8300 ?0184 83fc mar192 to mar255 reserved 0184 8400 ?0187 ffff ? reserved peripheral register descriptions 29 april 2004 ? revised january 2006 sprs247f table 2?5. quick dma (qdma) and pseudo registers hex address range acronym register name 0200 0000 qopt qdma options parameter register 0200 0004 qsrc qdma source address register 0200 0008 qcnt qdma frame count register 0200 000c qdst qdma destination address register 0200 0010 qidx qdma index register 0200 0014 ? 0200 001c reserved 0200 0020 qsopt qdma pseudo options register 0200 0024 qssrc qdma psuedo source address register 0200 0028 qscnt qdma psuedo frame count register 0200 002c qsdst qdma destination address register 0200 0030 qsidx qdma psuedo index register table 2?6. edma registers (c64x) hex address range acronym register name 01a0 0800 ? 01a0 ff98 ? reserved 01a0 ff9c eprh event polarity high register 01a0 ffa4 ciprh channel interrupt pending high register 01a0 ffa8 cierh channel interrupt enable high register 01a0 ffac ccerh channel chain enable high register 01a0 ffb0 erh event high register 01a0 ffb4 eerh event enable high register 01a0 ffb8 ecrh event clear high register 01a0 ffbc esrh event set high register 01a0 ffc0 pqar0 priority queue allocation register 0 01a0 ffc4 pqar1 priority queue allocation register 1 01a0 ffc8 pqar2 priority queue allocation register 2 01a0 ffcc pqar3 priority queue allocation register 3 01a0 ffdc eprl event polarity low register 01a0 ffe0 pqsr priority queue status register 01a0 ffe4 ciprl channel interrupt pending low register 01a0 ffe8 cierl channel interrupt enable low register 01a0 ffec ccerl channel chain enable low register 01a0 fff0 erl event low register 01a0 fff4 eerl event enable low register 01a0 fff8 ecrl event clear low register 01a0 fffc esrl event set low register 01a1 0000 ? 01a3 ffff ? reserved peripheral register descriptions 30 april 2004 ? revised january 2006 sprs247f table 2?7. edma parameter ram (c64x) ? hex address range acronym register name comments 01a0 0000 ? 01a0 0017 ? parameters for event 0 (6 words) parameters for event 0 (6 words) or reload/link parameters for other event 01a0 0018 ? 01a0 002f ? parameters for event 1 (6 words) 01a0 0030 ? 01a0 0047 ? parameters for event 2 (6 words) 01a0 0048 ? 01a0 005f ? parameters for event 3 (6 words) 01a0 0060 ? 01a0 0077 ? parameters for event 4 (6 words) 01a0 0078 ? 01a0 008f ? parameters for event 5 (6 words) 01a0 0090 ? 01a0 00a7 ? parameters for event 6 (6 words) 01a0 00a8 ? 01a0 00bf ? parameters for event 7 (6 words) 01a0 00c0 ? 01a0 00d7 ? parameters for event 8 (6 words) 01a0 00d8 ? 01a0 00ef ? parameters for event 9 (6 words) 01a0 00f0 ? 01a0 00107 ? parameters for event 10 (6 words) 01a0 0108 ? 01a0 011f ? parameters for event 11 (6 words) 01a0 0120 ? 01a0 0137 ? parameters for event 12 (6 words) 01a0 0138 ? 01a0 014f ? parameters for event 13 (6 words) 01a0 0150 ? 01a0 0167 ? parameters for event 14 (6 words) 01a0 0168 ? 01a0 017f ? parameters for event 15 (6 words) 01a0 0150 ? 01a0 0197 ? parameters for event 16 (6 words) 01a0 0168 ? 01a0 01af ? parameters for event 17 (6 words) ... ... 01a0 05d0 ? 01a0 05e7 ? parameters for event 62 (6 words) 01a0 05e8 ? 01a0 05ff ? parameters for event 63 (6 words) 01a0 0600 ? 01a0 0617 ? reload/link parameters for event 0 (6 words) reload/link parameters for other event 0?15 01a0 0618 ? 01a0 062f ? reload/link parameters for event 1 (6 words) ... ... 01a0 07e0 ? 01a0 07f7 ? reload/link parameters for event 20 (6 words) 01a0 07f8 ? 01a0 080f ? reload/link parameters for event 21 (6 words) 01a0 0810 ? 01a0 0827 ? reload/link parameters for event 22 (6 words) ... ... 01a0 13c8 ? 01a0 13df ? reload/link parameters for event 147 (6 words) 01a0 13e0 ? 01a0 13f7 ? reload/link parameters for event 148 (6 words) 01a0 13f8 ? 01a0 13ff ? scratch pad area (2 words) 01a0 1400 ? 01a3 ffff ? reserved ? the c6413/c6410 device has 213 edma parameters total: 64-event/reload channels and 149-reload only parameter sets [six (6) word s each] that can be used to reload/link edma transfers. peripheral register descriptions 31 april 2004 ? revised january 2006 sprs247f table 2?8. interrupt selector registers (c64x) hex address range acronym register name comments 019c 0000 muxh interrupt multiplexer high selects which interrupts drive cpu interrupts 10?15 (int10?int15) 019c 0004 muxl interrupt multiplexer low selects which interrupts drive cpu interrupts 4?9 (int04?int09) 019c 0008 extpol external interrupt polarity sets the polarity of the external interrupts (ext_int4?ext_int7) 019c 000c ? 019f ffff ? reserved table 2?9. device configuration registers hex address range acronym register name comments 01b3 f000 percfg peripheral configuration register enables or disables specific peripherals. this register is also used for power-down of disabled peripherals. 01b3 f004 devstat device status register read-only. provides status of the user?s device configuration on reset. 01b3 f008 jtagid jtag identification register read-only. provides 32-bit jtag id of the device. 01b3 f00c ? 01b3 f014 ? reserved 01b3 f018 pcfglock peripheral configuration lock register 01b3 f01c ? 01b3 ffff ? reserved peripheral register descriptions 32 april 2004 ? revised january 2006 sprs247f table 2?10. mcbsp 0 registers hex address range acronym register name comments 018c 0000 drr0 mcbsp0 data receive register via configuration bus the cpu and edma controller can only read this register; they cannot write to it. 0x3000 0000 ? 0x33ff ffff drr0 mcbsp0 data receive register via peripheral bus 018c 0004 dxr0 mcbsp0 data transmit register via configuration bus 0x3000 0000 ? 0x33ff ffff dxr0 mcbsp0 data transmit register via peripheral bus 018c 0008 spcr0 mcbsp0 serial port control register 018c 000c rcr0 mcbsp0 receive control register 018c 0010 xcr0 mcbsp0 transmit control register 018c 0014 srgr0 mcbsp0 sample rate generator register 018c 0018 mcr0 mcbsp0 multichannel control register 018c 001c rcere00 mcbsp0 enhanced receive channel enable register 0 018c 0020 xcere00 mcbsp0 enhanced transmit channel enable register 0 018c 0024 pcr0 mcbsp0 pin control register 018c 0028 rcere10 mcbsp0 enhanced receive channel enable register 1 018c 002c xcere10 mcbsp0 enhanced transmit channel enable register 1 018c 0030 rcere20 mcbsp0 enhanced receive channel enable register 2 018c 0034 xcere20 mcbsp0 enhanced transmit channel enable register 2 018c 0038 rcere30 mcbsp0 enhanced receive channel enable register 3 018c 003c xcere30 mcbsp0 enhanced transmit channel enable register 3 018c 0040 ? 018f ffff ? reserved table 2?11. mcbsp 1 registers hex address range acronym register name comments 0190 0000 drr1 mcbsp1 data receive register via configuration bus the cpu and edma controller can only read this register; they cannot write to it. 0x3400 0000 ? 0x37ff ffff drr1 mcbsp1 data receive register via peripheral bus 0190 0004 dxr1 mcbsp1 data transmit register via configuration bus 0x3400 0000 ? 0x37ff ffff dxr1 mcbsp1 data transmit register via peripheral bus 0190 0008 spcr1 mcbsp1 serial port control register 0190 000c rcr1 mcbsp1 receive control register 0190 0010 xcr1 mcbsp1 transmit control register 0190 0014 srgr1 mcbsp1 sample rate generator register 0190 0018 mcr1 mcbsp1 multichannel control register 0190 001c rcere01 mcbsp1 enhanced receive channel enable register 0 0190 0020 xcere01 mcbsp1 enhanced transmit channel enable register 0 0190 0024 pcr1 mcbsp1 pin control register 0190 0028 rcere11 mcbsp1 enhanced receive channel enable register 1 0190 002c xcere11 mcbsp1 enhanced transmit channel enable register 1 0190 0030 rcere21 mcbsp1 enhanced receive channel enable register 2 0190 0034 xcere21 mcbsp1 enhanced transmit channel enable register 2 0190 0038 rcere31 mcbsp1 enhanced receive channel enable register 3 0190 003c xcere31 mcbsp1 enhanced transmit channel enable register 3 0190 0040 ? 0193 ffff ? reserved peripheral register descriptions 33 april 2004 ? revised january 2006 sprs247f table 2?12. timer 0 registers hex address range acronym register name comments 0194 0000 ctl0 timer 0 control register determines the operating mode of the timer, monitors the timer status, and controls the function of the tout pin. 0194 0004 prd0 timer 0 period register contains the number of timer input clock cycles to count. this number controls the tstat signal frequency. 0194 0008 cnt0 timer 0 counter register contains the current value of the incrementing counter. 0194 000c ? 0197 ffff ? reserved table 2?13. timer 1 registers hex address range acronym register name comments 0198 0000 ctl1 timer 1 control register determines the operating mode of the timer, monitors the timer status, and controls the function of the tout pin. 0198 0004 prd1 timer 1 period register contains the number of timer input clock cycles to count. this number controls the tstat signal frequency. 0198 0008 cnt1 timer 1 counter register contains the current value of the incrementing counter. 0198 000c ? 019b ffff ? reserved table 2?14. timer 2 registers hex address range acronym register name comments 01ac 0000 ctl2 timer 2 control register determines the operating mode of the timer, monitors the timer status. 01ac 0004 prd2 timer 2 period register contains the number of timer input clock cycles to count. this number controls the tstat signal frequency. 01ac 0008 cnt2 timer 2 counter register contains the current value of the incrementing counter. 01ac 000c ? 01af ffff ? reserved peripheral register descriptions 34 april 2004 ? revised january 2006 sprs247f table 2?15. hpi registers hex address range acronym register name comments ? hpid hpi data register host read/write access only 0188 0000 hpic hpi control register hpic has both host/cpu read/write access 0188 0004 hpia (hpiaw) ? hpi address register (write) hpia has both host/cpu read/write access 0188 0008 hpia (hpiar) ? hpi address register (read) hpia has both host/cpu read/write access 0188 000c ? 0189 ffff ? reserved 018a 0000 hpi_trctl hpi transfer request control register 018a 0004 ? 018b ffff ? reserved ? host access to the hpia register updates both the hpiaw and hpiar registers. the cpu can access hpiaw and hpiar independently. table 2?16. gp0 registers hex address range acronym register name 01b0 0000 gpen gp0 enable register 01b0 0004 gpdir gp0 direction register 01b0 0008 gpval gp0 value register 01b0 000c ? reserved 01b0 0010 gpdh gp0 delta high register 01b0 0014 gphm gp0 high mask register 01b0 0018 gpdl gp0 delta low register 01b0 001c gplm gp0 low mask register 01b0 0020 gpgc gp0 global control register 01b0 0024 gppol gp0 interrupt polarity register 01b0 0028 ? 01b3 efff ? reserved peripheral register descriptions 35 april 2004 ? revised january 2006 sprs247f table 2?17. mcasp0 and mcasp1 control registers hex address range acronym register name mcasp0 mcasp1 acronym register name 01b4 c000 01b5 0000 pid peripheral identification register [register value: 0x0010 0101] 01b4 c004 01b5 0004 pwrdemu power down and emulation management register 01b4 c008 01b5 0008 ? reserved 01b4 c00c 01b5 000c ? reserved 01b4 c010 01b5 0010 pfunc pin function register 01b4 c014 01b5 0014 pdir pin direction register 01b4 c018 01b5 0018 pdout pin data out register 01b4 c01c 01b5 001c pdin/pdset pin data in / data set register read returns: pdin writes affect: pdset 01b4 c020 01b5 0020 pdclr pin data clear register 01b4 c024 ? 01b4 c040 01b5 0024 ? 01b5 0040 ? reserved 01b4 c044 01b5 0044 gblctl global control register 01b4 c048 01b5 0048 amute mute control register 01b4 c04c 01b5 004c dlbctl digital loop-back control register 01b4 c050 01b5 0050 ditctl dit mode control register 01b4 c054 ? 01b4 c05c 01b5 0054 ? 01b5 005c ? reserved 01b4 c060 01b5 0060 rgblctl alias of gblctl containing only receiver reset bits, allows transmit to be reset independently from receive. 01b4 c064 01b5 0064 rmask receiver format unit bit mask register 01b4 c068 01b5 0068 rfmt receive bit stream format register 01b4 c06c 01b5 006c afsrctl receive frame sync control register 01b4 c070 01b5 0070 aclkrctl receive clock control register 01b4 c074 01b5 0074 ahclkrctl high-frequency receive clock control register 01b4 c078 01b5 0078 rtdm receive tdm slot 0?31 register 01b4 c07c 01b5 007c rintctl receiver interrupt control register 01b4 c080 01b5 0080 rstat status register ? receiver 01b4 c084 01b5 0084 rslot current receive tdm slot register 01b4 c088 01b5 0088 rclkchk receiver clock check control register 01b4 c08c ? 01b4 c09c 01b5 008c ? 01b5 009c ? reserved 01b4 c0a0 01b5 00a0 xgblctl alias of gblctl containing only transmitter reset bits, allows transmit to be reset independently from receive. 01b4 c0a4 01b5 00a4 xmask transmit format unit bit mask register 01b4 c0a8 01b5 00a8 xfmt transmit bit stream format register 01b4 c0ac 01b5 00ac afsxctl transmit frame sync control register 01b4 c0b0 01b5 00b0 aclkxctl transmit clock control register 01b4 c0b4 01b5 00b4 ahclkxctl high-frequency transmit clock control register 01b4 c0b8 01b5 00b8 xtdm transmit tdm slot 0?31 register 01b4 c0bc 01b5 00bc xintctl transmit interrupt control register 01b4 c0c0 01b5 00c0 xstat status register ? transmitter 01b4 c0c4 01b5 00c4 xslot current transmit tdm slot 01b4 c0c8 01b5 00c8 xclkchk transmit clock check control register peripheral register descriptions 36 april 2004 ? revised january 2006 sprs247f table 2?17. mcasp0 and mcasp1 control registers (continued) hex address range register name acronym mcasp0 register name acronym mcasp1 01b4 c0cc ? 01b4 c0fc 01b5 00cc ? 01b5 00fc ? reserved 01b4 c100 01b5 0100 ditcsra0 left (even tdm slot) channel status register file 01b4 c104 01b5 0104 ditcsra1 left (even tdm slot) channel status register file 01b4 c108 01b5 0108 ditcsra2 left (even tdm slot) channel status register file 01b4 c10c 01b5 010c ditcsra3 left (even tdm slot) channel status register file 01b4 c110 01b5 0110 ditcsra4 left (even tdm slot) channel status register file 01b4 c114 01b5 0114 ditcsra5 left (even tdm slot) channel status register file 01b4 c118 01b5 0118 ditcsrb0 right (odd tdm slot) channel status register file 01b4 c11c 01b5 011c ditcsrb1 right (odd tdm slot) channel status register file 01b4 c120 01b5 0120 ditcsrb2 right (odd tdm slot) channel status register file 01b4 c124 01b5 0124 ditcsrb3 right (odd tdm slot) channel status register file 01b4 c128 01b5 0128 ditcsrb4 right (odd tdm slot) channel status register file 01b4 c12c 01b5 012c ditcsrb5 right (odd tdm slot) channel status register file 01b4 c130 01b5 0130 ditudra0 left (even tdm slot) user data register file 01b4 c134 01b5 0134 ditudra1 left (even tdm slot) user data register file 01b4 c138 01b5 0138 ditudra2 left (even tdm slot) user data register file 01b4 c13c 01b5 013c ditudra3 left (even tdm slot) user data register file 01b4 c140 01b5 0140 ditudra4 left (even tdm slot) user data register file 01b4 c144 01b5 0144 ditudra5 left (even tdm slot) user data register file 01b4 c148 01b5 0148 ditudrb0 right (odd tdm slot) user data register file 01b4 c14c 01b5 014c ditudrb1 right (odd tdm slot) user data register file 01b4 c150 01b5 0150 ditudrb2 right (odd tdm slot) user data register file 01b4 c154 01b5 0154 ditudrb3 right (odd tdm slot) user data register file 01b4 c158 01b5 0158 ditudrb4 right (odd tdm slot) user data register file 01b4 c15c 01b5 015c ditudrb5 right (odd tdm slot) user data register file 01b4 c160 ? 01b4 c17c 01b5 0160 ? 01b5 017c ? reserved 01b4 c180 01b5 0180 srctl0 serializer 0 control register 01b4 c184 01b5 0184 srctl1 serializer 1 control register 01b4 c188 01b5 0188 srctl2 serializer 2 control register 01b4 c18c 01b5 018c srctl3 serializer 3 control register 01b4 c190 01b5 0190 srctl4 serializer 4 control register 01b4 c194 01b5 0194 srctl5 serializer 5 control register 01b4 c198 01b5 0198 ? reserved 01b4 c19c 01b5 019c ? reserved 01b4 c1a0 ? 01b4 c1fc 01b5 01a0 ? 01b5 01fc ? reserved 01b4 c200 01b5 0200 xbuf0 transmit buffer for serializer 0 01b4 c204 01b5 0204 xbuf1 transmit buffer for serializer 1 01b4 c208 01b5 0208 xbuf2 transmit buffer for serializer 2 01b4 c20c 01b5 020c xbuf3 transmit buffer for serializer 3 01b4 c210 01b5 0210 xbuf4 transmit buffer for serializer 4 01b4 c214 01b5 0214 xbuf5 transmit buffer for serializer 5 peripheral register descriptions 37 april 2004 ? revised january 2006 sprs247f table 2?17. mcasp0 and mcasp1 control registers (continued) hex address range register name acronym mcasp0 register name acronym mcasp1 01b4 c218 01b5 0218 ? reserved 01b4 c21c 01b5 021c ? reserved 01b4 c220 ? 01b4 c27c 01b5 0220 ? 01b5 027c ? reserved 01b4 c280 01b5 0280 rbuf0 receive buffer for serializer 0 01b4 c284 01b5 0284 rbuf1 receive buffer for serializer 1 01b4 c288 01b5 0288 rbuf2 receive buffer for serializer 2 01b4 c28c 01b5 028c rbuf3 receive buffer for serializer 3 01b4 c290 01b5 0290 rbuf4 receive buffer for serializer 4 01b4 c294 01b5 0294 rbuf5 receive buffer for serializer 5 01b4 c298 01b5 0298 ? reserved 01b4 c29c 01b5 029c ? reserved 01b4 c2a0 ? 01b4 ffff 01b5 02a0 ? 01b5 3fff ? reserved table 2?18. mcasp0 data registers hex address range acronym register name comments 3c00 0000 ? 3c0f ffff rbuf/xbufx mcaspx receive buffers or mcaspx transmit buffers via the peripheral data bus. (used when rsel or xsel bits = 0 [these bits are located in the rfmt or xfmt registers, respectively].) table 2?19. mcasp1 data registers hex address range acronym register name comments 3c10 0000 ? 3c1f ffff rbuf/xbufx mcaspx receive buffers or mcaspx transmit buffers via the peripheral data bus. (used when rsel or xsel bits = 0 [these bits are located in the rfmt or xfmt registers, respectively].) peripheral register descriptions 38 april 2004 ? revised january 2006 sprs247f table 2?20. i2c0 and i2c1 registers hex address range acronym register name i2c0 i2c1 acronym register name 01b4 0000 01b4 4000 i2coarx i2cx own address register 01b4 0004 01b4 4004 i2cimrx i2cx interrupt mask/status register 01b4 0008 01b4 4008 i2cstrx i2cx interrupt status register 01b4 000c 01b4 400c i2cclklx i2cx clock low-time divider register 01b4 0010 01b4 4010 i2cclkhx i2cx clock high-time divider register 01b4 0014 01b4 4014 i2ccntx i2cx data count register 01b4 0018 01b4 4018 i2cdrrx i2cx data receive register 01b4 001c 01b4 401c i2csarx i2cx slave address register 01b4 0020 01b4 4020 i2cdxrx i2cx data transmit register 01b4 0024 01b4 4024 i2cmdrx i2cx mode register 01b4 0028 01b4 4028 i2civrx i2cx interrupt vector register 01b4 002c 01b4 402c i2cemdrx i2cx extended mode register 01b4 0030 01b4 4030 i2cpscx i2cx prescaler register 01b4 0034 01b4 4034 i2cpid1x i2cx peripheral identification register 1 [value: 0x0000 0105 ] 01b4 0038 01b4 4038 i2cpid2x i2cx peripheral identification register 2 [value: 0x0000 0005 ] 01b4 003c ? 01b4 0044 01b4 403c ? 01b4 4044 ? reserved 01b4 0048 01b4 4048 i2cpfuncx i2cx pin function register 01b4 004c 01b4 404c i2cpdirx i2cx pin direction register 01b4 0050 01b4 4050 i2cpdinx i2cx pin data in register 01b4 0054 01b4 4054 i2cpdoutx i2cx pin data out register 01b4 0058 01b4 4058 i2cpdsetx i2cx pin data set register 01b4 005c 01b4 405c i2cpdclrx i2cx pin data clear register 01b4 0060 ? 01b4 3fff 01b4 4060 ? 01b4 7fff ? reserved edma channel synchronization events 39 april 2004 ? revised january 2006 sprs247f 2.7 edma channel synchronization events the c64x edma supports up to 64 edma channels which service peripheral devices and external memory. table 2?21 lists the source of c64x edma synchronization events associated with each of the programmable edma channels. for the c6413/c6410 device, the association of an event to a channel is fixed; each of the edma channels has one specific event associated with it. these specific events are captured in the edma event registers (erl, erh) even if the events are disabled by the edma event enable registers (eerl, eerh). the priority of each event can be specified independently in the transfer parameters stored in the edma parameter ram. for more detailed information on the edma module and how edma events are enabled, captured, processed, linked, chained, and cleared, etc., see the tms320c6000 dsp enhanced direct memory access (edma) controller reference guide (literature number spru234). table 2?21. tms320c6413/c6410 edma channel synchronization events ? edma channel event name event description 0 dsp_int hpi-to-dsp interrupt 1 tint0 timer 0 interrupt 2 tint1 timer 1 interrupt 3 sd_inta emifa sdram timer interrupt 4 gpint4/ext_int4 gp0 event 4/external interrupt pin 4 5 gpint5/ext_int5 gp0 event 5/external interrupt pin 5 6 gpint6/ext_int6 gp0 event 6/external interrupt pin 6 7 gpint7/ext_int7 gp0 event 7/external interrupt pin 7 8 gpint0 gp0 event 0 9 gpint1 gp0 event 1 10 gpint2 gp0 event 2 11 gpint3 gp0 event 3 12 xevt0 mcbsp0 transmit event 13 revt0 mcbsp0 receive event 14 xevt1 mcbsp1 transmit event 15 revt1 mcbsp1 receive event 16?18 ? none 19 tint2 timer 2 interrupt 20?27 ? none 28 ? none 29 ? none 30?31 ? none 32 axevte0 mcasp0 transmit even event 33 axevto0 mcasp0 transmit odd event 34 axevt0 mcasp0 transmit event 35 arevte0 mcasp0 receive even event 36 arevto0 mcasp0 receive odd event 37 arevt0 mcasp0 receive event 38 axevte1 mcasp1 transmit even event 39 axevto1 mcasp1 transmit odd event 40 axevt1 mcasp1 transmit event ? in addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. for more detailed information on edma event-transfer chaining, see the tms320c6000 dsp enhanced direct memory access (edma) controller reference guide (literature number spru234). interrupt sources and interrupt selector 40 april 2004 ? revised january 2006 sprs247f table 2?21. tms320c6413/c6410 edma channel synchronization events ? (continued) edma channel event description event name 41 arevte1 mcasp1 receive even event 42 arevto1 mcasp1 receive odd event 43 arevt1 mcasp1 receive event 44 icrevt0 i2c0 receive event 45 icxevt0 i2c0 transmit event 46 icrevt1 i2c1 receive event 47 icxevt1 i2c1 transmit event 48 gpint8 gp0 event 8 49 gpint9 gp0 event 9 50 gpint10 gp0 event 10 51 gpint11 gp0 event 11 52 gpint12 gp0 event 12 53 gpint13 gp0 event 13 54 gpint14 gp0 event 14 55 gpint15 gp0 event 15 56?63 ? none ? in addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. for more detailed information on edma event-transfer chaining, see the tms320c6000 dsp enhanced direct memory access (edma) controller reference guide (literature number spru234). 2.8 interrupt sources and interrupt selector the c64x dsp core supports 16 prioritized interrupts, which are listed in table 2?22. the highest-priority interrupt is int_00 (dedicated to reset) while the lowest-priority interrupt is int_15. the first four interrupts (int_00?int_03) are non-maskable and fixed. the remaining interrupts (int_04?int_15) are maskable and default to the interrupt source specified in table 2?22. the interrupt source for interrupts 4?15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the interrupt selector control registers: muxh (address 0x019c0000) and muxl (address 0x019c0004). interrupt sources and interrupt selector 41 april 2004 ? revised january 2006 sprs247f table 2?22. c6413/c6410 dsp interrupts cpu interrupt number interrupt selector control register selector value (binary) interrupt event interrupt source int_00 ? ? ? reset int_01 ? ? ? nmi int_02 ? ? ? reserved reserved. do not use. int_03 ? ? ? reserved reserved. do not use. int_04 ? muxl[4:0] 00100 gpint4/ext_int4 gp0 interrupt 4/external interrupt pin 4 int_05 ? muxl[9:5] 00101 gpint5/ext_int5 gp0 interrupt 5/external interrupt pin 5 int_06 ? muxl[14:10] 00110 gpint6/ext_int6 gp0 interrupt 6/external interrupt pin 6 int_07 ? muxl[20:16] 00111 gpint7/ext_int7 gp0 interrupt 7/external interrupt pin 7 int_08 ? muxl[25:21] 01000 edma_int edma channel (0 through 63) interrupt int_09 ? muxl[30:26] 01001 emu_dtdma emu dtdma int_10 ? muxh[4:0] 00011 sd_inta emifa sdram timer interrupt int_11 ? muxh[9:5] 01010 emu_rtdxrx emu real-time data exchange (rtdx) receive int_12 ? muxh[14:10] 01011 emu_rtdxtx emu rtdx transmit int_13 ? muxh[20:16] 00000 dsp_int hpi-to-dsp interrupt int_14 ? muxh[25:21] 00001 tint0 timer 0 interrupt int_15 ? muxh[30:26] 00010 tint1 timer 1 interrupt ? ? 01100 xint0 mcbsp0 transmit interrupt ? ? 01101 rint0 mcbsp0 receive interrupt ? ? 01110 xint1 mcbsp1 transmit interrupt ? ? 01111 rint1 mcbsp1 receive interrupt ? ? 10000 gpint0 gp0 interrupt 0 ? ? 10001 reserved reserved. do not use. ? ? 10010 reserved reserved. do not use. ? ? 10011 tint2 timer 2 interrupt ? ? 10100 reserved reserved. do not use. ? ? 10101 reserved reserved. do not use. ? ? 10110 icint0 i2c0 interrupt ? ? 10111 icint1 i2c1 interrupt ? ? 11000 axint1 mcasp1 transmit interrupt ? ? 11001 arint1 mcasp1 receive interrupt ? ? 11010 reserved reserved. do not use. ? ? 11011 reserved reserved. do not use. ? ? 11100 axint0 mcasp0 transmit interrupt ? ? 11101 arint0 mcasp0 receive interrupt ? ? 11110 reserved reserved. do not use. ? ? 11111 reserved reserved. do not use. ? interrupts int_00 through int_03 are non-maskable and fixed. ? interrupts int_04 through int_15 are programmable by modifying the binary selector values in the interrupt selector control reg isters fields. table 2?22 shows the default interrupt sources for interrupts int_04 through int_15. for more detailed information on interrupt sources and selection, see the tms320c6000 dsp interrupt selector reference guide (literature number spru646). signal groups description 42 april 2004 ? revised january 2006 sprs247f 2.9 signal groups description trst gp0[7]/ext_int7 ? ieee standard 1149.1 (jtag) emulation reserved reset and interrupts control/status tdi tdo tms tck emu0 emu1 nmi gp0[6]/ext_int6 ? gp0[5]/ext_int5 ? gp0[4]/ext_int4 ? reset rsv rsv clock/pll and oscillator clkin clkmode3 clkmode2 pllv emu2 emu3 emu4 emu5 gp0 general-purpose input/output 0 (gp0) port gp0[7]/ext_int7 ? gp0[6]/ext_int6 ? gp0[5]/ext_int5 ? gp0[4]/ext_int4 ? gp0[3] clkout6/gp0[2] ? clkout4/gp0[1] ? gp0[0] clkout6/gp0[2] ? clkout4/gp0[1] ? emu6 emu7 emu8 emu9 emu10 hd15/gp0[15] hd14/gp0[14] hd13/gp0[13] hd12/gp0[12] hd11/gp0[11] hd10/gp0[10] hd9/gp0[9] hd8/gp0[8] ? these pins are muxed with the gp0 pins and by default these signals function as clocks (clkout4 or clkout6). to use these muxed pins as gpio signals, the appropriate gpio register bits (gpxen and gpxdir) must be properly enabled and configured. for more details, see the device configurations section of this data sheet. ? these pins are gp0 pins that can also function as external interrupt sources (ext_int[7:4]). default after reset is ext_intx or gpio as input-only. these pins are muxed with the hpi peripheral pins and by default these signals function as hpi. for more details on these muxed pins, see the device configurations section of this data sheet. rsv emu11 rsv rsv rsv rsv rsv rsv oscin oscout oscv dd oscv ss clkmode1 clkmode0 clkinsel w w w osc_dis figure 2?6. cpu and peripheral signals signal groups description 43 april 2004 ? revised january 2006 sprs247f ace3 aeclkout1 aed[31:0] ace2 ace1 ace0 aea[22:3] aardy data memory map space select address byte enables 32 20 external memory i/f control emifa (32-bit) aeclkin ahold aholda abusreq bus arbitration aare /asdcas /asads /asr e asdcke aeclkout2 asoe3 abe3 abe2 abe1 abe0 aaoe /asdras /asoe aawe /asdwe /aswe apdt hhwil/afsr1[2] ? hcntl0/afsr1[1] ? hcntl1 data register select half-word select control hpi ? (host-port interface) 32 hd[29:16]/mcasp1 ? has /aclkr1[1] ? hr/w /afsr1[3] ? hcs /aclkr1[2] ? hds1 /aclkr1[3] ? hds2 hrdy hint (hpi16 only) hd[7:0] hd[15:8]/gp0[15:8] ? hd[31,30] ? these hpi pins are muxed with the mcasp1 or gp0 peripherals. by default, these signals function as hpi and no function, respectively. for more details on these muxed pins, see the device configurations section of this data sheet. figure 2?7. peripheral signals signal groups description 44 april 2004 ? revised january 2006 sprs247f mcbsps (multichannel buffered serial ports) clkx0 fsx0 dx0 clkr0 fsr0 dr0 clks0 transmit mcbsp0 receive clock clkx1 fsx1 dx1 clkr1 fsr1 dr1 clks1 transmit mcbsp1 receive clock tout0 timers tinp0 tout1/lendian timer 1 tinp1 timer 2 timer 0 scl0 i2c0 i2cs sda0 scl1 i2c1 sda1 figure 2?7. peripheral signals (continued) signal groups description 45 april 2004 ? revised january 2006 sprs247f mcasp0 (multichannel audio serial port 0) aclkx0 ahclkx0 transmit clock generator amutein0 auto mute logic amute0 afsx0 transmit frame sync afsr0 receive frame sync axr0[5] axr0[4] aclkr0 ahclkr0 receive clock generator axr0[3] axr0[2] axr0[1] axr0[0] 6-serial ports flexible partitioning tx, rx, off transmit clock check circuit receive clock check circuit error detect (see note a) (transmit/receive data pins) (transmit/receive data pins) (receive bit clock) (transmit bit clock) (receive master clock) (transmit master clock) (receive frame sync or left/right clock) (transmit frame sync or left/right clock) notes: a. the mcasps? error detect function detects underruns, overruns, early/late frame syncs, dma errors, and external mute in put. b. bolded and italicized text within parentheses denotes the function of the pins in an audio system. figure 2?7. peripheral signals (continued) signal groups description 46 april 2004 ? revised january 2006 sprs247f mcasp1 (multichannel audio serial port 1) hd24/aclkx1 hd27/ahclkx1 transmit clock generator hd29/amutein1 auto mute logic hd28/amute1 hd22/afsx1 transmit frame sync hd23/afsr1 receive frame sync hd21/axr1[5] hd20/axr1[4] hd25/aclkr1 hd26/ahclkr1 receive clock generator hd19/axr1[3] hd18/axr1[2] hd17/axr1[1] hd16/axr1[0] 6-serial ports flexible partitioning tx, rx, off transmit clock check circuit receive clock check circuit error detect (see note a) (transmit/receive data pins) (transmit/receive data pins) (receive bit clock) (transmit bit clock) (receive master clock) (transmit master clock) (receive frame sync or left/right clock) (transmit frame sync or left/right clock) notes: a. the mcasps? error detect function detects underruns, overruns, early/late frame syncs, dma errors, and external mute in put. b. bolded and italicized text within parentheses denotes the function of the pins in an audio system. hcntl0/afsr1[1] hhwil/afsr1[2] hr/w /afsr1[3] has /aclkr1[1] hcs /aclkr1[2] hds1 /aclkr1[3] afcmux[1:0] (percfg[10:9]) afcmux[1:0] (percfg[10:9]) figure 2?7. peripheral signals (continued) device configurations 47 april 2004 ? revised january 2006 sprs247f 3 device configurations on the c6413/c6410 device, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the peripheral configurations register (percfg) [address location 0x01b3f000] after device reset. 3.1 device configuration at device reset table 3?1 describes the c6413/c6410 device configuration pins. the logic level of the aea[22:19], tout1/lendian, tout0/hpi_en , and hd5 pins is latched at reset to determine the device configuration. the logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., fpga/cpld) to intelligently drive these pins. when using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. the clkinsel and osc_dis configuration pins should remain driven to the correct levels during device operation and must only be changed when reset is low. the device configuration pins are sampled during reset and are driven after the reset is removed. at this time, the control device should ensure it has stopped driving the device configuration pins of the dsp to again avoid contention. note: if a configuration pin must be routed out from the device, the internal pullup/pulldown (ipu/ipd) resistor should not be relied upon. ti recommends the use of an external pullup/pulldown resistor. device configurations 48 april 2004 ? revised january 2006 sprs247f table 3?1. c6413/c6410 device configuration pins ( tout1/ lendian, aea[22:19], tout0/ hpi_en , hd5, clkinsel, and osc_dis) configuration pin no. ipd/ipu ? functional description tout1/ lendian aa1 ipu device endian mode (lend) 0 ? system operates in big endian mode 1 ? system operates in little endian mode (default) aea[22:21] [m21, n21] ipd bootmode [1:0] 00 ? no boot (default mode) 01 ? hpi boot (based on hpi_en pin) 10 ? reserved 11 ? emifa 8-bit rom boot aea[20:19] [p22, n22] ipd emifa input clock select clock mode select for emifa (aeclkin_sel[1:0]) 00 ? aeclkin (default mode) 01 ? cpu/4 clock rate 10 ? cpu/6 clock rate 11 ? reserved tout0/ hpi_en aa2 ipd hpi, mcasp1, gp0[15:8] select selects whether the hpi peripheral or mcasp1 peripheral, and gp0[15:8] pins are functionally enabled 0 ? hpi is enabled and the mcasp1 peripheral and gp0 [15:8] pins are disabled (default mode); [hpi32, if hd5 = 1; hpi16 if hd5 = 0] 1 ? hpi i is disabled and the mcasp1 peripheral and gp0 [15:8] pins are enabled for more detail on the peripherals (mcasp1 and gp0[15:8] pins) muxed with hpi, see the table 3?2. hd5 y13 ipu hpi peripheral bus width (hpi_width) select 0 ? hpi operates as an hpi16. (hpi bus is 16 bits wide. hd[15:0] pins are used for hpi and the remaining hd[31:16] muxed pins function as mcasp1 peripheral pins or are reserved pins in the hi-z state.) 1 ? hpi operates as an hpi32. (hpi bus is 32 bits wide. all hd[31:0] pins are used for host-port operations.) for more detail on the peripherals (mcasp1 and gp0[15:8] pins) muxed with hpi, see the table 3?2. clkinsel a11 ipu pll input clock source select selects whether the pll input clock is clkin [pin high] or directly from the crystal oscillator (oscin and oscout) [pin low]. for proper device operation, this pin must be used in conjunction with the osc_dis pin. 0 ? oscillator pads (oscin, oscout directly from the crystal oscillator) for proper device operation, osc_dis must be 0 1 ? clkin square wave (default) for proper device operation, osc_dis must be 1 this pin must be pulled to the correct level even after reset. osc_dis b7 ipu oscillator disable selects whether the oscillator is enabled or disabled. for proper device operation, this pin must follow the clkinsel pin operation. 0 ? osc enabled 1 ? osc disabled (default) this pin must be pulled to the correct level even after reset. ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) device configurations 49 april 2004 ? revised january 2006 sprs247f 3.2 peripheral configuration at device reset some c6413/c6410 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., hpi, general-purpose input/output 0 pins gp0[15:8], and mcasp1). ? hpi, mcasp1, and gp0 peripherals the tout0/ hpi_en (aa2 pin) is latched at reset. this pin selects whether the hpi peripheral or mcasp1 peripheral, and gp0[15:8] pins are functionally enabled (see table 3?2). table 3?2. tout0/ hpi_en and hd5 peripheral selection (hpi or mcasp1 and select gp0 pins) ? peripheral selection peripherals selected hpi_en (aa2) hd5 [hpi_width] (y13) hpi mcasp1 gp0 [15:8] description 0 0 16-bit hpi available n/a ? hpi_en = 0, hd5 = hpi16 is enabled and mcasp1 peripheral is enabled and gp0 [15:8] pins are disabled. all multiplexed hpi/mcasp1 pins function as mcasp1 pins. all multiplexed hpi/gp0 are reserved pins in the hi-z state. 0 1 32-bit hpi n/a ? n/a ? hpi_en = 0, hd5 = hpi32 is enabled and mcasp1 peripheral and gp0 [15:8] pins are disabled. all multiplexed hpi/mcasp1 and hpi/gp0 pins function as hpi pins. 1 x n/a ? available available hpi_en = hpi is disabled and the mcasp1 peripheral and gp0 [15:8] pins are enabled. all multiplexed hpi/mcasp1 and hpi/gp0 pins function as mcasp1 and gp0 pins, respectively. to use the gp0 pins, the appropriate bits in the gp0en and gp0dir registers need to be set. all standalone hpi pins are reserved pins in the hi-z state ? the tout0/hpi_en pin has an internal pulldown that enables the hpi by default. the t out0/hpi_en pin can disable the hpi via an external pullup resistor or be driven high during reset. the tout0/hpi_en pin is not software-controllable. ? n/a = not available device configurations 50 april 2004 ? revised january 2006 sprs247f 3.3 peripheral selection after device reset hpi, mcbsp1, mcbsp0, mcasp1, mcasp0, i2c1, and i2c0 the c6413/c6410 device has designated registers for peripheral configuration (percfg), device status (devstat), and jtag identification (jtagid). these registers are part of the device configuration module and are mapped to a 4k block memory starting at 0x01b3f000. the cpu accesses these registers via the cfgbus. the peripheral configuration register (percfg), allows the user to control the peripheral selection of the mcasp1, mcasp0, i2c1, and i2c0 peripherals. for more detailed information on the percfg register control bits, see figure 3?1 and table 3?3. 31 28 27 24 reserved ? reserved ? r-0 r-0 23 16 reserved ? r-0 15 11 10 9 8 reserved ? afcmux[1:0] mcasp1en r-0 r/w-0 r/w-0 76543 21 0 i2c1en reserved ? reserved ? reserved ? i2c0en mcbsp1en mcbsp0en mcasp0en r/w-0 r-0 r-0 r-0 r/w-0 r-1 r-1 r/w-0 legend: r = read only; r/w = read/write; -n = value after reset ? for proper device operation, all reserved bits have to be written with ?0?. figure 3?1. peripheral configuration register (percfg) [address location: 0x01b3f000] device configurations 51 april 2004 ? revised january 2006 sprs247f table 3?3. peripheral configuration (percfg) register selection bit descriptions bit name description 31:11 reserved reserved. read-only, for proper device operation, all reserved bits have to be written with ?0?. 10:9 afcmux[1:0] clocks and frame syncs select bits. determines which of the clock and frame sync pairs are input to mcasp1. 00 = aclkr1, afsr1 pins (default). 01 = aclkr1[1], afsr1[1] pins 10 = aclkr1[2], afsr1[2] pins 11 = aclkr1[3], afsr1[3] pins [designed for multiple non-simultaneous i2s sources with different clock sources]. 8 mcasp1en mcasp1 select bit. selects whether the mcasp1 peripheral is enabled or disabled (default). (this feature allows power savings by disabling the peripheral when not in use.) 0 = mcasp1 is disabled and the module is powered down [default]. 1 = mcasp1 is enabled. 7 i2c1en inter-integrated circuit 1 (i2c1) enable bit. selects whether i2c1 peripheral is enabled or disabled (default). (this feature allows power savings by disabling the peripheral when not in use.) 0 = i2c1 is disabled, and the module is powered down (default). 1 = i2c1 is enabled. 6:4 reserved reserved. read-only, for proper device operation, all reserved bits have to be written with ?0?. 3 i2c0en inter-integrated circuit 0 (i2c0) enable bit. selects whether i2c0 peripheral is enabled or disabled (default). (this feature allows power savings by disabling the peripheral when not in use.) 0 = i2c0 is disabled, and the module is powered down (default). 1 = i2c0 is enabled. 2 mcbsp1en mcbsp1 enable bit. this bit is read-only as a ?1? (mcbsp1 always enabled). 1 mcbsp0en mcbsp0 enable bit . this bit is read-only as a ?1? (mcbsp0 always enabled). 0 mcasp0en mcasp0 select bit. selects whether the mcasp0 peripheral is enabled or disabled. (this feature allows power savings by disabling the peripheral when not in use.) 0 = mcasp0 is disabled. 1 = mcasp0 is enabled. device configurations 52 april 2004 ? revised january 2006 sprs247f 3.4 peripheral configuration lock by default, the mcasp1, mcasp0, i2c1, and i2c0 peripherals are disabled on power up. in order to use these peripherals on the c6413/c6410 device, the peripheral must first be enabled in the peripheral configuration register (percfg). software muxed pins should not be programmed to switch functionalities during run-time. care should also be taken to ensure that no accesses are being performed before disabling the peripherals. to help minimize power consumption in the c6413/c6410 device, unused peripherals may be disabled.. figure 3?2 shows the flow needed to enable (or disable) a given peripheral on the c6413/c6410 device. unlock the percfg register using the pcfglock register write to percfg register to enable/disable peripherals read from percfg register wait 128 cpu cycles before accessing enabled peripherals figure 3?2. peripheral enable/disable flow diagram a 32-bit key (value = 0x10c0010c) must be written to the peripheral configuration lock register (pcfglock) in order to unlock access to the percfg register. reading the pcfglock register determines whether the percfg register is currently locked (lockstat bit = 1) or unlocked (lockstat bit = 0), see figure 3?3. a peripheral can only be enabled when the percfg register is ?unlocked? (lockstat bit = 0). device configurations 53 april 2004 ? revised january 2006 sprs247f read accesses 31 10 reserved lockstat r-0 r-1 write accesses 31 0 lock w-0 legend: r = read only; r/w = read/write; -n = value after reset figure 3?3. pcfglock register diagram [address location: 0x01b3 f018] ? read/write accesses table 3?4. pcfglock register selection bit descriptions ? read accesses bit name description 31:1 reserved reserved. read-only, writes have no effect. 0 lockstat lock status bit. determines whether the percfg register is locked or unlocked. 0 = unlocked, read accesses to the percfg register allowed. 1 = locked, write accesses to the percfg register do not modify the register state [default]. reads are unaffected by lock status. table 3?5. pcfglock register selection bit descriptions ? write accesses bit name description 31:0 lock lock bits. 0x10c0010c = unlocks percfg register accesses. any write to the percfg register will automatically relock the register. in order to avoid the unnecessary overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the percfg register with the necessary enable bits set. prior to waiting 128 cpu cycles, the percfg register should be read. there is no direct correlation between the cpu issuing a write to the percfg register and the write actually occurring. reading the percfg register after the write is issued forces the cpu to wait for the write to the percfg register to occur. once a peripheral is enabled, the dsp (or other peripherals such as the hpi) must wait a minimum of 128 cpu cycles before accessing the enabled peripheral. the user must ensure that no accesses are performed to a peripheral while it is disabled. in addition to the normal usage, the pcfglock register can be used to override the power saver settings specified in the percfg register. when the power saver feature is disabled (pcfglock written with 0xc0100c01), all peripherals controlled by percfg are enabled. if the power saver is returned to normal operation (pcfglock written with 0x0c01 c010), then the peripherals return to the operating condition specified by percfg. t urning off the power saver settings will add a worst-case 50 mw of power to the overall dsp power consumption. note: overriding the settings of the percfg register will not cause a conflict on the multiplexed pins. for example, with the hpi and mcasp1 peripherals, the hpi will still have control over the multiplexed pins provided the tout0/hpi_en pin was ?0? at reset. device configurations 54 april 2004 ? revised january 2006 sprs247f 3.5 device status register description the device status register depicts the status of the device peripheral selection. once set, these bits will remain set until a device reset; therefore, these bits should be masked when reading the devstat register since their values can change. for the actual register bit names and their associated bit field descriptions, see figure 3?4 and table 3?6. 31 24 reserved r-100x0111 23 19 18 17 16 pllm reserved osc ext res clkinsel r-xxxxx r- 1 r-x r-x 15 14 13 12 11 10 9 8 reserved clkmode3 reserved hpi-width reserved hpi_en r-000 r-x r-0 r-x r-0 r-x 76543 210 clkmode2 clkmode1 clkmode0 lendian bootmode1 bootmode0 aeclkinsel1 aeclkinsel0 r-x r-x r-x r-x r-x r-x r-x r-x legend: r = read only; r/w = read/write; -n = value after reset figure 3?4. device status register (devstat) description ? 0x01b3 f004 table 3?6. device status (devstat) register selection bit descriptions bit name description 31:24 reserved reserved. read-only, writes have no effect. 23:19 pllm pll multiply factor status bits. shows the status of the pll multiply mode selected; whether the cpu clock frequency equals the input clock frequency x1 (bypass), x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24. for more detailed information on the pll multiply factors, see the clock pll and oscillator section of this data sheet. 18 reserved reserved. read-only, writes have no effect. 17 osc ext res oscillator external resistor status bit. shows the status internal or external of the osc bias resistor. 0 = normal functional mode with interna l bias resistor. 1 = normal functional mode with external bias resistor [default; internally tied high]. 16 clkinsel pll input clock select status bit. shows the status of whether the pll input clock is clkin [pin high] or directly from the crystal oscillator (oscin and oscout) [pin low] 0 = crystal oscillator (oscin and oscout). 1 = clkin (default). 15:13 reserved reserved. read-only, writes have no effect. 11 reserved reserved. read-only, writes have no effect. 10 hpi_width hpi bus width control bit. shows the status of whether the hpi bus operates in 32-bit mode or in 16-bit mode (default). 0 = hpi operates in 16-bit mode. (default). 1 = hpi operates in 32-bit mode. 9 reserved reserved. read-only, writes have no effect. 8 hpi_en hpi_en pin status bit. shows the status at device reset of the hpi_en pin, which controls the hpi peripheral as enabled [default] or disabled. 0 = hpi_en pin is low, meaning the hpi peripheral is enabled (default). 1 = hpi_en pin is high, meaning the hpi peripheral is disabled. device configurations 55 april 2004 ? revised january 2006 sprs247f table 3?6. device status (devstat) register selection bit descriptions (continued) description name bit 12 clkmode3 clock mode select status bits shows the status (?1 or 0?) of the clkmode[3:0] select bits: 7 clkmode2 shows the status (?1 or 0?) of the clkmode[3:0] select bits: clock mode select for cpu clock frequency (clkmode[3:0]), for example: 6 clkmode1 clock mode select for cpu clock frequency (clkmode[3:0]), for example: 0000? bypass (x1) (default mode) for more details on the clkmode pins and the pll multiply factors, see the clock pll section of this 5 clkmode0 0000? bypass (x1) (default mode) for more details on the clkmode pins and the pll multiply factors, see the clock pll section of this data sheet. 4 lendian device endian mode (lendian) shows the status of whether the system is operating in big endian mode or little endian mode (default). 0 ? system is operating in big endian mode 1 ? system is operating in little endian mode (default) 3 bootmode1 bootmode configuration bits (aea[22:21] pins) shows the status of what device bootmode configuration is operational. bootmode [1:0] 00 ? no boot (default mode) 2 bootmode0 00 ? no boot (default mode) 01 ? hpi boot (based on hpi_en pin) 10 ? reserved 11 ? emifa 8-bit rom boot 1 aeclkinsel1 emifa input clock select (aea[20:19] pins) shows the status of what clock mode is enabled or disabled for the emif. clock mode select for emifa (aeclkin_sel[1:0]) 00 ? aeclkin (default mode) 0 aeclkinsel0 00 ? aeclkin (default mode) 01 ? cpu/4 clock rate 10 ? cpu/6 clock rate 11 ? reserved 3.6 jtag id register description the jtag id register is a read-only register that identifies to the customer the jtag/device id. for the c6413/c6410 device, the jtag id register resides at address location 0x01b3 f008. the register hex value for the c6413/c6410 device is: 0x0007 902f. for the actual register bit names and their associated bit field descriptions, see figure 3?5 and table 3?7. 31?28 27?12 11?1 0 variant (4-bit) part number (16-bit) manufacturer (11-bit) lsb r-0000 r-0000 0000 1000 0100 r-0000 0010 111 r-1 legend: r = read only; -n = value after reset figure 3?5. jtag id register description ? tms320c6413/c6410 register value ? 0x0007 902f table 3?7. jtag id register selection bit descriptions bit name description 31:28 variant variant (4-bit) value. c6413/c6410 value: 0000. 27:12 part number part number (16-bit) value. c6413/c6410 value: 0000 0000 1000 0100. 11?1 manufacturer manufacturer (11-bit) value. c6413/c6410 value: 0000 0010 111. 0 lsb lsb. this bit is read as a ?1? for c6413/c6410. device configurations 56 april 2004 ? revised january 2006 sprs247f 3.7 multiplexed pins multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. those muxed pins that are configured by software should not be programmed to switch functionalities during run-time. those muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. table 3?8 identifies the multiplexed pins on the c6413/c6410 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions. table 3?8. c6413/c6410 device multiplexed pins multiplexed pins ipd/ipu ? default default description name no. ipd/ipu ? default function default setting description clkout4/gp0[1] a2 ipu clkout4 gp1en = 0 (disabled) these pins are software-configurable. to use these pins as gpio pins, the gpxen bits in the gpio enable register and the gpxdir bits in the gpio direction register must be properly clkout6/gp0[2] b3 ipu clkout6 gp2en = 0 (disabled) the gpio direction register must be properly configured. gpxen = 1: gpx pin enabled gpxdir = 0: gpx pin is an input gpxdir = 1: gpx pin is an output hcntl0/afsr1[1] y6 by default, hpi32 is enabled upon reset hhwil/afsr1[2] y7 by default, hpi32 is enabled upon rese t (mcasp1 is disabled). hr/w /afsr1[3] aa5 (mcasp1 is disabled). to enable the mcasp1 peripheral, the has /aclkr1[1] y5 to enable the mcasp1 peripheral, the tout0/ hpi_en pin must be high at reset eithe r via an external pullup (pu) resistor (1 k ? ) or hcs /aclkr1[2] aa11 via an external pullup (pu) resistor (1 k ? ) o r driven by a control device (disabling the hpi). hds1 /aclkr1[3] ab11 hpi pin function tout0/ hpi_en = 0 driven by a control device (disabling the hpi). hd29/amutein1 w11 ipu hpi pin function tout0/ hpi_en = 0 32-bit hpi enabled) or the mcasp1 peripheral pins can be used if the hpi is used as a 16-bit width [hpi_en = 0, hd28/amute1 w10 ipu hhwil pin 32-bit hpi enabled) hpi is used as a 16-bit width [hpi_en = 0 , hd5 = the clocks and frame syncs select bits hd26/ahclkr1 ab4 (hpi16 only) mcasp1 pins disabled. the clocks and frame syncs select bit s (afcmux[1:0]) located in the percfg register hd25/aclkr1 aa9 (afcmux[1:0]) located in the percfg register determine which of the clock and frame sync hd24/aclkx1 aa4 determine which of the clock and frame sync pairs are input to mcasp1. for more detailed information, see the device configuration hd23/afsr1 ab9 pairs are input to mcasp1. for more detailed information, see the device configuration section of this data sheet. hd22/afsx1 ab5 section of this data sheet. hd21/axr1[5] y9 by default, hpi32 is enabled upon rese t (mcasp1 is disabled). to enable the mcasp1 peripheral, the hd20/axr1[4] ab8 (mcasp1 is disabled). to enable the mcasp1 peripheral, the tout0/ hpi_en pin must be high at reset eithe r via an external pullup (pu) resistor (1 k ? ) or hd19/axr1[3] aa6 ipu hpi pin tout0/ hpi_en = 0 32-bit hpi enabled) via an external pullup (pu) resistor (1 k ? ) or driven by a control device (disabling the hpi). hd18/axr1[2] ab7 ipu hpi pin function 32-bit hpi enabled) mcasp1 pins disabled. or the mcasp1 peripheral pins can be used if the hpi is used as a 16-bit width [hpi_en = 0 , hd5 = mcasp1 pin direction is controlled by the hd16/axr1[0] ab6 mcasp1 pin direction is controlled by the pdir[x] bits in the mcasp1pdir register. mcasp1pdir = 0 input, = 1 output configuration examples 57 april 2004 ? revised january 2006 sprs247f table 3?8. c6413/c6410 device multiplexed pins (continued) description default setting default function ipd/ipu ? multiplexed pins description default setting default function ipd/ipu ? no. name hd15/gp0[15] y12 by default, hpi is enabled upon reset (gp0[15:9] hd14/gp0[14] aa12 by default, hpi is enabled upon reset (gp0[15:9] pins are disabled). to use gp0[15:9] as gpio pins, the hpi needs hd13/gp0[13 ] ab13 hpi_en = 0 ), hd12/gp0[12] y14 ipu hpi pin hpi_en = 0 32-bit hpi enabled) to be disabled (hpi_en = 1 ), the gpxen bits in the gpio enable register and hd11/gp0[11] ab14 ipu hpi pin function 32-bit hpi enabled) gpio pins disabled. the gpxen bits in the gpio enable register and the gpxdir bits in the gpio direction registe r must be properly configured. hd10/gp0[10] aa15 function gpio pins disabled. the gpxdir bits in the gpio direction register must be properly configured. gpxen = 1: gpx pin enabled hd9/gp0[9] y16 gpxen = 1: gpx pin enabled gpxdir = 0: gpx pin is an input hd8/gp0[8] ab16 gpxdir = 0: gpx pin is an input gpxdir = 1: gpx pin is an output ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) 3.8 debugging considerations it is recommended that external connections be provided to device configuration pins, including tout1/lendian, aea[22:19], tout0/hpi_en , clkinsel, and osc_dis. although internal pullup/pulldown resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. note: if a configuration pin must be routed out from the device, the internal pullup/pulldown (ipu/ipd) resistor should not be relied upon. ti recommends the use of an external pullup/pulldown resistor. 3.9 configuration examples figure 3?6 illustrates an example of peripheral selections/options that are configurable on the c6413/c610 device. configuration examples 58 april 2004 ? revised january 2006 sprs247f clkout4, clkout6, pllv, clkin, clkmode[3:0], osc_dis, clkinsel, oscin, oscout, oscv dd , oscv ss percfg register value: 0x0000_018f [cpu/4 option [default] and afsr1, aclkr1 pins selected] external pins: tout0/ hpi_en = 0; hd5 = 0 (ipu) mcasp0 mcasp1 hpi (16-bit) mcbsp0 mcbsp1 emifa clock and system gp0 and ext_int i2c0 i2c1 timer0 timer1 timer2 aed[31:0] 32 aeclkin, aardy, ahold aea[22:3], ace[3:0] , abe[3:0] , aeclkout1, aeclkout2, asdcke, asoe3 , apdt , aholda , abusreq, aare /asdcas /asads /asre , aaoe /asdras /asoe , aawe /asdwe /aswe scl0 sda0 tinp0 tout0 tinp1 tout1/lendian gp0[ 3:0] gp0[7:4] hd[15:0] scl1 sda1 ahclkx0, afsx0, aclkx0, amute0, amutein0, ahclkr0, afsr0, aclkr0 axr0[5:0] ahclkx1, afsx1, aclkx1, amute1, amutein1, ahclkr1, afsr1, afsr1[1], afsr1[2], afsr1[3], aclkr1, aclkr1[1], aclkr1[2], aclkr1[3] axr1[5:0] clkr1, fsr1, dr1, clks1, dx1, fsx1, clkx1 clkr0, fsr0, dr0, clks0, dx0, fsx0, clkx0 16 hcntl0, hcntl1, hhwil, has , hr/w , hcs , hds1 , hds2 figure 3?6. configuration example a (hpi16 + 2 mcasps + 2 mcbsps +2 i2cs + emif + 3 timers + gpio) terminal functions 59 april 2004 ? revised january 2006 sprs247f 3.10 terminal functions the terminal functions table (table 3?9) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (i, o/z, or i/o/z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. for more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the device configurations section of this data sheet. terminal functions 60 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions signal type ? ipd/ ipu ? description name no. type ? ipd/ ipu ? description clock/pll configuration clkin a12 i ipd clock input. this clock is the input to the on-chip pll. clkout4/gp0[1] a2 i/o/z ipu clock output at 1/4 of the device speed ( o/z ) [default] or this pin can be programmed as a gp0 1 pin ( i/o/z ). clkout6/gp0[2] b3 i/o/z ipu clock output at 1/6 of the device speed ( o/z ) [default] or this pin can be programmed as a gp0 2 pin ( i/o/z ). clkinsel a11 i ipu clkin select. selects whether the pll input clock is clkin [pin high] or directly from the crystal oscillator (oscin and oscout) [pin low]. for proper device operation, this pin must be used in conjunction with the osc_dis pin. clkmode3 c11 i ipd clock mode selects selects whether the cpu clock frequency = input clock frequency x1 (bypass), x5, clkmode2 b10 i ipd clock mode selects ? selects whether the cpu clock frequency = input clock frequency x1 (bypass), x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24. clkmode1 a13 i ipd x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24. for more details on the clkmode pins and the pll multiply factors, see the clock clkmode0 c13 i ipd for more details on the clkmode pins and the pll multiply factors, see the clock pll section of this data sheet. pllv ? c12 a pll voltage supply oscin a6 i ? crystal oscillator input (xi) oscout a7 o ? crystal oscillator output (xo) oscv dd b6 s ? power for crystal oscillator (1.2 v), do not connect to board power cv dd ; for optimum performance, connected internally. if clkin is used instead of the oscillator, then this pin can be left open or connected to cv dd . oscv ss c6 gnd ? ground for crystal oscillator, do not connect to board ground; for optimum performance, connected internally. if clkin is used instead of the oscillator, then this pin can be left open or connected to v ss . osc_dis b7 i ipu oscillator disable select. for proper device operation, this pin must follow the clkinsel pin operation. 0 ? osc enabled; clkinsel must be 0 1 ? osc disabled (default); clkinsel must be 1 jtag emulation tms u3 i ipu jtag test-port mode select tdo t4 o/z ipu jtag test-port data out tdi t1 i ipu jtag test-port data in tck t2 i ipu jtag test-port clock trst u1 i ipd jtag test-port reset. for ieee 1149.1 jt ag compatibility, see the ieee 1149.1 jtag compatibility statement portion of this data sheet. emu0 r1 i/o/z ipu emulation pin 0 # emu1 t3 i/o/z ipu emulation pin 1 # ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. ? pllv is not part of external voltage supply. see the clock pll and oscillator section for information on how to connect this pi n. # the emu0 and emu1 pins are internally pulled up with 30-k ? resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. however, for boundary scan operation, pull down the emu1 and emu0 pins with a dedicate d 1-k ? resistor. terminal functions 61 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) name no. type ? ipd/ ipu ? description jtag emulation (continued) emu2 r2 i/o/z ipu emulation pin 2. reserved for future use, leave unconnected. emu3 u2 i/o/z ipu emulation pin 3. reserved for future use, leave unconnected. emu4 r3 i/o/z ipu emulation pin 4. reserved for future use, leave unconnected. emu5 p2 i/o/z ipu emulation pin 5. reserved for future use, leave unconnected. emu6 r4 i/o/z ipu emulation pin 6. reserved for future use, leave unconnected. emu7 v2 i/o/z ipu emulation pin 7. reserved for future use, leave unconnected. emu8 v1 i/o/z ipu emulation pin 8. reserved for future use, leave unconnected. emu9 v3 i/o/z ipu emulation pin 9. reserved for future use, leave unconnected. emu10 w3 i/o/z ipu emulation pin 10. reserved for future use, leave unconnected. emu11 w2 i/o/z ipu emulation pin 11. reserved for future use, leave unconnected. resets, interrupts, and general-purpose input/outputs reset c9 i device reset nmi b9 i ipd nonmaskable interrupt, edge-driven (rising edge). any noise on the nmi pin may trigger an nmi interrupt; therefore, if the nmi pin is not used, it is recommended that the nmi pin be grounded versus relying on the ipd. gp0[7]/ext_int7 y1 i/o/z ipu general-purpose input/output (gpio) pins ( i/o/z ) or external interrupts ( input only ) . the default after reset setting is gpio enabled as input-only. gp0[6]/ext_int6 c4 i/o/z ipu general-purpose input/output (gpio) pins ( i/o/z ) or external interrupts ( input only ). the default after reset setting is gpio enabled as input-only. ? when these pins function as external interrupts [by selecting the corresponding gp0[5]/ext_int5 b4 i/o/z ipu ? when these pins function as external interrupts [by selecting the corresponding interrupt enable register bit (ier.[7:4])], they are edge-driven and the polarity can be independently selected via the external interrupt polarity register bits gp0[4]/ext_int4 a4 i/o/z ipu independently selected via the external interrupt polarity register bits (extpol.[3:0]). hd15/gp0[15] y12 hd14/gp0[14] aa12 hd13/gp0[13 ] ab13 hd12/gp0[12] y14 i/o/z ipu host-port data pins ( i/o/z ) [default] or general-purpose input/output (gp0) [15:8] pin s ( i/o/z ) hd11/gp0[11] ab14 i/o/z ipu host-port data pins ( i/o/z ) [default] or general-purpose input/output (gp0) [15:8] pins ( i/o/z ) hd10/gp0[10] aa15 gp0 [3:0] pins ( i/o/z ) hd9/gp0[9] y16 gp0 [3:0] pins ( i/o/z ) clock output at 1/6 of the device speed ( o/z ) [default] or this pin can be programmed a s a gp0 2 pin ( i/o/z ). hd8/gp0[8] ab16 clock output at 1/6 of the device speed ( o/z ) [default] or this pin can be programmed as a gp0 2 pin ( i/o/z ). clock output at 1/4 of the device speed ( o/z ) [default] or this pin can be programmed as gp0[3] b13 i/o/z ipd clock output at 1/4 of the device speed ( o/z ) [default] or this pin can be programmed as a gp0 1 pin ( i/o/z ). clkout6/gp0[2] b3 i/o/z ipu a gp0 1 pin ( i/o/z ). clkout4/gp0[1] a2 i/o/z ipu gp0[0] d13 i/o/z ipd ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. terminal functions 62 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) name description ipd/ ipu ? type ? no. emifa (32-bit) ? control signals common to all types of memory ace3 h19 o/z ipu emifa memory space enables ace2 n20 o/z ipu emifa memory space enables ? enabled by bits 28 through 31 of the word address ace1 r20 o/z ipu ? enabled by bits 28 through 31 of the word address ? only one pin is asserted during any external data access ace0 f20 o/z ipu ? only one pin is asserted during any external data access abe3 ab21 o/z ipu emifa byte-enable control decoded from the low-order address bits. the number of address bits or byte abe2 p21 o/z ipu emifa byte-enable control ? decoded from the low-order address bits. the number of address bits or byte enables used depends on the width of external memory. abe1 a22 o/z ipu enables used depends on the width of external memory. ? byte-write enables for most types of memory abe0 d16 o/z ipu ? byte-write enables for most types of memory ? can be directly connected to sdram read and write mask signal (sdqm) apdt t19 o/z ipu emifa peripheral data transfer, allows direct transfer between external peripherals emifa (32-bit) ? bus arbitration aholda j21 o ipu emifa hold-request-acknowledge to the host ahold j22 i ipu emifa hold request from the host abusreq r19 o ipu emifa bus request output emifa (32-bit) ? asynchronous/synchronous memory control aeclkin k22 i ipd emifa external input clock. the emifa input clock (aeclkin, cpu/4 clock, or cpu/6 clock) is selected at reset via the pullup/pulldown resistors on the aea[20:19] pins. aeclkin is the default for the emifa input clock. aeclkout2 u22 o/z ipd emifa output clock 2. programmable to be emif a input clock (aeclkin, cpu/4 clock, or cpu/6 clock) frequency divided-by-1, -2, or -4. aeclkout1 f22 o/z ipd emifa output clock 1 [at emifa input clock (aeclkin, cpu/4 clock, or cpu/6 clock) frequency]. aare / asdcas / asads /asre d20 o/z ipu emifa asynchronous memory read-enable/sdram column-address strobe/programmable synchronous interface-address strobe or read-enable ? for programmable synchronous interface, the renen field in the ce space secondary control register (cexsec) selects between asads and asre : if renen = 0, then the asads /asre signal functions as the asads signal. if renen = 1, then the asads /asre signal functions as the asre signal. aaoe / asdras / asoe e20 o/z ipu emifa asynchronous memory output-enable/sdram row-address strobe/programmable synchronous interface output-enable aawe / asdwe / aswe c20 o/z ipu emifa asynchronous memory write-enable/sdram write-enable/programmable synchronous interface write-enable asdcke k21 o/z ipu emifa sdram clock-enable (used for self-refresh mode). ? if sdram is not in system, asdcke can be used as a general-purpose output. asoe3 p19 o/z ipu emifa synchronous memory output-enable for ace3 (for glueless fifo interface) aardy l21 i ipu asynchronous memory ready input ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. terminal functions 63 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) name description ipd/ ipu ? type ? no. emifa (32-bit) ? address aea22 m21 emifa external address (word address) aea21 n21 i/o/z ipd emifa external address (word address) note: emif address numbering for the c6413/c6410 devices starts with aea3 to maintain signal name compatibility with other c64x devices (e.g., c6411, c6414, aea20 p22 i/o/z ipd note: emif address numbering for the c6413/c6410 devices starts with aea3 to maintain signal name compatibility with other c64x ? devices (e.g., c6411, c6414 , c6415, and c6416) [see the 64-bit emif adressing scheme in the tms320c6000 dsp aea19 n22 c6415, and c6416) [see the 64-bit emif adressing scheme in the tms320c6000 dsp external memory interface (emif) reference guide (literature number spru266)]. aea18 h22 external memory interface (emif) reference guide (literature number spru266)]. note: if a configuration pin must be routed out from the device, the internal aea17 h21 note: if a configuration pin must be routed out from the device, the interna l pullup/pulldown (ipu/ipd) resistor should not be relied upon. ti recommends the use of aea16 j20 pullup/pulldown (ipu/ipd) resistor should not be relied upon. ti recommends the use of an external pullup/pulldown resistor. aea15 h20 an external pullup/pulldown resistor. also controls initialization of dsp modes at reset ( i ) via pullup/pulldown resistors aea14 g20 ? also controls initialization of dsp modes at reset ( i ) via pullup/pulldown resistors ? boot mode (aea[22:21]): aea13 k20 ? boot mode (aea[22:21]): 00 ? no boot (default mode) aea12 b21 00 ? no boot (default mode) 01 ? hpi boot (based on hpi_en pin) 10 ? reserved aea11 b22 o/z ipd 01 ? hpi boot (based on hpi_en pin) 10 ? reserved 11 ? emifa 8-bit rom boot aea10 d21 o/z ipd 11 ? emifa 8-bit rom boot aea9 d22 ? emif clock select aea8 e21 ? emif clock select ? aea[20:19]: clock mode select for emifa (aeclkin_sel[1:0]) aea7 e22 ? aea[20:19]: clock mode select for emifa (aeclkin_sel[1:0]) 00 ? aeclkin (default mode) aea6 f21 00 ? aeclkin (default mode) 01 ? cpu/4 clock rate 10 ? cpu/6 clock rate aea5 m20 10 ? cpu/6 clock rate 11 ? reserved aea4 j19 11 ? reserved for more details, see the device configurations section of this data sheet. aea3 l20 for more details, see the device configurations section of this data sheet. emifa (32-bit) ? data aed31 w21 aed30 w22 aed29 v20 aed28 w20 aed27 aa22 aed26 y20 aed25 aa21 aed24 ab22 aed23 p20 i/o/z ipu emifa external data aed22 r22 i/o/z ipu emifa external data aed21 r21 aed20 u21 aed19 v21 aed18 t20 aed17 v22 aed16 u20 aed15 a18 aed14 d17 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. terminal functions 64 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) name description ipd/ ipu ? type ? no. emifa (32-bit) ? data (continued) aed13 b18 aed12 c18 aed11 a19 aed10 c19 aed9 b19 aed8 a21 aed7 d15 i/o/z ipu emifa external data aed6 a15 i/o/z ipu emifa external data aed5 b15 aed4 c15 aed3 a16 aed2 c16 aed1 b16 aed0 c17 timer 2 ? no external pins. the timer 2 peripheral pins are not pinned out as external pins. timer 1 tout1/lendian aa1 i/o/z ipu timer 1 output ( o/z ) or device endian mode ( i ). also controls initialization of dsp modes at reset via pullup/pulldown resistors ? device endian mode 0 ? big endian 1 ? little endian (default) for more details on lendian, see the device configurations section of this data sheet. tinp1 ab1 i ipd timer 1 or general-purpose input timer 0 tout0/hpi_en aa2 i/o/z ipd timer 0 output pin and hpi enable hpi_en pin function the hpi_en pin function selects whether the hpi peripheral or mcasp1 peripheral, and gp0[15:8] pins are functionally enabled 0 ? hpi is enabled and the mcasp1 peripheral and gp0 [15:8] pins are disabled (default mode); [hpi32, if hd5 = 1; hpi16 if hd5 = 0] 1 ? hpi i is disabled and the mcasp1 peripheral and gp0 [15:8] pins are enabled for more details, see the device configurations section of this data sheet. tinp0 ab2 i ipd timer 0 or general-purpose input inter-integrated circuit 1 (i2c1) scl1 aa18 i/o/z ? i2c1 clock. when the i2c module is used, use an external pullup resistor on this pin. sda1 aa19 i/o/z ? i2c1 data. when i2c is used, ensure there is an external pullup resistors on this pin. inter-integrated circuit 0 (i2c0) scl0 ab18 i/o/z ? i2c0 clock. when i2c is used, ensure there is an external pullup resistors on this pin. sda0 ab19 i/o/z ? i2c0 data. when i2c is used, ensure there is an external pullup resistors on this pin. ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. terminal functions 65 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) name description ipd/ ipu ? type ? no. multichannel buffered serial port 1 (mcbsp1) clkr1 g3 i/o/z ipd mcbsp1 receive clock fsr1 g2 i/o/z ipd mcbsp1 receive frame sync dr1 f1 i ipd mcbsp1 receive data clks1 g1 i ipd mcbsp1 external clock source (as opposed to internal) dx1 h2 o/z ipd mcbsp1 transmit data fsx1 h3 i/o/z ipd mcbsp1 transmit frame sync clkx1 h1 i/o/z ipd mcbsp1 transmit clock multichannel buffered serial port 0 (mcbsp0) clkr0 c2 i/o/z ipd mcbsp0 receive clock fsr0 d1 i/o/z ipd mcbsp0 receive frame sync dr0 d2 i ipd mcbsp0 receive data clks0 d3 i ipd mcbsp0 external clock source (as opposed to internal) dx0 e2 o/z ipd mcbsp0 transmit data fsx0 e4 i/o/z ipd mcbsp0 transmit frame sync clkx0 e3 i/o/z ipd mcbsp0 transmit clock multichannel audio serial port 0 (mcasp0) ahclkx0 n1 i/o/z ipd mcasp0 transmit high-frequency master clock. afsx0 m2 i/o/z ipd mcasp0 transmit frame sync or left/right clock (lrclk). aclkx0 m1 i/o/z ipd mcasp0 transmit bit clock. amute0 k4 i/o/z ipd mcasp0 mute output. amutein0 j4 i ipd mcasp0 mute input. ahclkr0 l1 i/o/z ipd mcasp0 receive high-frequency master clock. afsr0 k2 i/o/z ipd mcasp0 receive frame sync or left/right clock (lrclk). aclkr0 k1 i/o/z ipd mcasp0 receive bit clock. axr0[5] p3 mcasp0 tx/rx data pin [5]. axr0[4] n3 mcasp0 tx/rx data pin [4]. axr0[3] m3 i/o/z ipd mcasp0 tx/rx data pins [3]. axr0[2] l3 i/o/z ipd mcasp0 tx/rx data pin [2]. axr0[1] k3 mcasp0 tx/rx data pin [1]. axr0[0] l2 mcasp0 tx/rx data pins[0]. ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. terminal functions 66 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) name description ipd/ ipu ? type ? no. mcasp1 hcntl0/afsr1[1] y6 host control ? selects between control, address, or data registers ( i ) [default] or mcasp1 receive frame sync input 1 ( i ). hhwil/afsr1[2] y7 i ipu host half-word select ? first or second half-word (not necessarily high or low order) [for hpi16 bus width selection only] ( i ) [default] oror mcasp1 receive frame sync input 2 ( i ) . hr/w /afsr1[3] aa5 i ipu host read or write select ( i ) [default] or mcasp1 receive frame sync input 3 ( i ). has /aclkr1[1] y5 host address strobe ( i ) [default] or mcasp1 receive clock input 1 ( i ). hcs /aclkr1[2] aa11 host chip select ( i ) [default] or mcasp1 receive clock input 2 ( i ). hds1 /aclkr1[3] ab11 host data strobe 1 ( i ) [default] or mcasp1 receive clock input 3 ( i ). hd27/ahclkx1 y4 i/o/z ipu host-port data pin 27 ( i/o/z ) [default] or mcasp1 transmit high-frequency master clock ( i/o/z ). hd22/afsx1 ab5 i/o/z ipu host-port data pin 22 ( i/o/z ) [default] or mcasp1 transmit frame sync or left/right clock (lrclk) ( i/o/z ) . hd24/aclkx1 aa4 i/o/z ipu host-port data pin 24 ( i/o/z ) [default] or mcasp1 transmit bit clock ( i/o/z ). hd28/amute1 w10 i/o/z ipu host-port data pin 28 ( i/o/z ) [default] or mcasp1 mute output ( i/o/z ). hd29/amutein1 w11 i ipu host-port data pin 29 ( i/o/z ) [default] or mcasp1 mute input ( i ). hd26/ahclkr1 ab4 i/o/z ipu host-port data pin 26 ( i/o/z ) [default] or mcasp1 receive high-frequency master clock ( i/o/z ). hd23/afsr1 ab9 i/o/z ipu host-port data pin 23 ( i/o/z ) [default] or mcasp1 receive frame sync or left/right clock (lrclk) ( i/o/z ). hd25/aclkr1 aa9 i/o/z ipu host-port data pin 25 ( i/o/z ) [default] or mcasp1 receive bit clock ( i/o/z ). hd21/axr1[5] y9 hd20/axr1[4] ab8 hd19/axr1[3] aa6 i/o/z ipu host-port data pins [21:16] ( i/o/z ) [default] or mcasp1 tx/rx data pins [5:0] ( i/o/z ). hd18/axr1[2] ab7 i/o/z ipu host-port data pins [21:16] ( i/o/z ) [default] or mcasp1 tx/rx data pins [5:0] ( i/o/z ) . hd17/axr1[1] aa7 hd16/axr1[0] ab6 host-port interface (hpi) hint aa8 o/z ipu host interrupt from dsp to host ( o ) hcntl1 w7 i ipu host control ? selects between control, address, or data registers ( i ) hcntl0/afsr1[1] y6 host control ? selects between control, address, or data registers ( i ) [default] or mcasp1 receive frame sync input 1 ( i ). hhwil/afsr1[2] y7 i ipu host half-word select ? first or second half-word (not necessarily high or low order) [for hpi16 bus width selection only] ( i ) [default] or mcasp1 receive frame sync input 2 ( i ). hr/w /afsr1[3] aa5 i ipu host read or write select ( i ) [default] or mcasp1 receive frame sync input 3 ( i ). has /aclkr1[1] y5 host address strobe ( i ) [default] or mcasp1 receive clock input 1 ( i ). hcs /aclkr1[2] aa11 host chip select ( i ) [default] or mcasp1 receive clock input 2 ( i ). hds1 /aclkr1[3] ab11 host data strobe 1 ( i ) [default] or mcasp1 receive clock input 3 ( i ). hds2 ab12 i ipu host data strobe 2 ( i ) hrdy y10 o/z ipu host ready from dsp to host ( o ) ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. terminal functions 67 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) name description ipd/ ipu ? type ? no. host-port interface (hpi) (continued) hd31 y8 i/o/z ipu host-port data pin 31 ( i/o/z ) hd30 y11 i/o/z ipu host-port data pin 30 ( i/o/z ) hd29/amutein1 w11 i ipu host-port data pin 29 ( i/o/z ) [default] or mcasp1 mute input ( i ). hd28/amute1 w10 i/o/z ipu host-port data pin 28 ( i/o/z ) [default] or mcasp1 mute output ( i/o/z ). hd27/ahclkx1 y4 i/o/z ipu host-port data pin 27 ( i/o/z ) [default] or mcasp1 transmit high-frequency master clock ( i/o/z ). hd26/ahclkr1 ab4 i/o/z ipu host-port data pin 26 ( i/o/z ) [default] or mcasp1 receive high-frequency master clock ( i/o/z ). hd25/aclkr1 aa9 i/o/z ipu host-port data pin 25 ( i/o/z ) [default] or mcasp1 receive bit clock ( i/o/z ). hd24/aclkx1 aa4 i/o/z ipu host-port data pin 24 ( i/o/z ) [default] or mcasp1 transmit bit clock ( i/o/z ). hd23/afsr1 ab9 i/o/z ipu host-port data pin 23 ( i/o/z ) [default] or mcasp1 receive frame sync or left/right clock (lrclk) ( i/o/z ). hd22/afsx1 ab5 i/o/z ipu host-port data pin 22 ( i/o/z ) [default] or mcasp1 transmit frame sync or left/right clock (lrclk) ( i/o/z ). hd21/axr1[5] y9 hd20/axr1[4] ab8 hd19/axr1[3] aa6 i/o/z ipu host-port data [21:16] pin ( i/o/z ) [default] or mcasp1 tx/rx data pins [5:0] ( i/o/z ). hd18/axr1[2] ab7 i/o/z ipu host-port data [21:16] pin ( i/o/z ) [default] or mcasp1 tx/rx data pins [5:0] ( i/o/z ). hd17/axr1[1] aa7 hd16/axr1[0] ab6 hd15/gp0[15] y12 hd14/gp0[14] aa12 hd13/gp0[13 ] ab13 hd12/gp0[12] y14 i/o/z ipu host-port data [15:8] pins ( i/o/z ) [default] or general-purpose input/output (gp0) [15:8] hd11/gp0[11] ab14 i/o/z ipu host-port data [15:8] pins ( i/o/z ) [default] or general-purpose input/output (gp0) [15:8] pins ( i/o/z ). hd10/gp0[10] aa15 pins ( i/o/z ). hd9/gp0[9] y16 hd8/gp0[8] ab16 hd7 w12 host-port data [7:0] pins ( i/o/z ) hd6 aa13 host-port data [7:0] pins ( i/o/z ) host-port bus width user-configurable at device reset via a 1-k ? pullup/ hd5 y13 host-port bus width user-configurable at device reset via a 1-k ? pullup/ pulldown resistor on the hd5 pin ( i ): hd4 aa14 i/o/z ipu pulldown resistor on the hd5 pin ( i ): hd5 pin = 0: hpi operates as an hpi16. hd3 ab15 i/o/z ipu hd5 pin = 0: hpi operates as an hpi16. (hpi bus is 16 bits wide. hd[15:0] pins are used and the remaining hd[31:16] pins hd2 aa16 (hpi bus is 16 bits wide. hd[15:0] pins are used and the remaining hd[31:16] pins are reserved pins in the high-impedance state.) hd1 y15 are reserved pins in the high-impedance state.) hd5 pin = 1: hpi operates as an hpi32. hd0 w15 hd5 pin = 1: hpi operates as an hpi32. (hpi bus is 32 bits wide. all hd[31:0] pins are used for host-port operations.) ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. terminal functions 68 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) signal type ? ipd/ ipu ? description name no. type ? ipd/ ipu ? description reserved for test rsv u4 a ? reserved. this pin must be connected directly to cv dd for proper device operation. rsv f3 a ? reserved. this pin must be connected directly to dv dd for proper device operation. rsv c8 i ipd reserved. this pin must be connected directly to v ss for proper device operation. b11 a ? b12 i ? reserved (leave unconnected, do not connect to power or ground). if the signal must rsv c10 o ipu reserved (leave unconnected, do not connect to power or ground). if the signal must be routed from the device, the internal pull?up/down resistance should not be relied upon and an external pull?up/down should be used. rsv d7 o/z ? be routed from the device, the internal pull?up/down resistance should not be relied upon and an external pull?up/down should be used. d8 o/z ? supply voltage pins a3 a5 a8 a9 a14 a17 a20 b1 c22 e1 g22 dv dd j1 s 3.3-v supply voltage dv dd m22 s 3.3-v supply voltage p1 t22 w1 y2 y17 y19 y22 ab3 ab10 ab17 ab20 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) terminal functions 69 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) signal description ipd/ ipu ? type ? name description ipd/ ipu ? type ? no. supply voltage pins (continued) d5 d6 d9 d11 d12 d14 d18 e19 f19 g4 cv dd h4 s 1.2-v supply voltage (-400, -500 devices) cv dd l19 s 1.2-v supply voltage (-400, -500 devices) m4 m19 n4 v4 v19 w5 w9 w13 w16 w18 ground pins a1 a10 b2 b5 b8 v ss b14 gnd ground pins v ss b17 gnd ground pins b20 c1 c3 c5 c7 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) terminal functions 70 april 2004 ? revised january 2006 sprs247f table 3?9. terminal functions (continued) signal description ipd/ ipu ? type ? name description ipd/ ipu ? type ? no. ground pins (continued) c14 c21 d4 d10 d19 f2 f4 g19 g21 j2 j3 k19 l4 l22 n2 v ss n19 gnd ground pins v ss p4 gnd ground pins t21 u19 w4 w6 w8 w14 w17 w19 y3 y18 y21 aa3 aa10 aa17 aa20 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) development support 71 april 2004 ? revised january 2006 sprs247f 3.11 development support in case the customer would like to develop their own features and software on the tms320c6413/c6410 device, ti of fers an extensive line of development tools for the tms320c6000 ? dsp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the tool?s support documentation is electronically available within the code composer studio ? integrated development environment (ide). the following products support development of c6000 ? dsp-based applications: software development tools: code composer studio ? integrated development environment (ide): including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp/bios ? ), which provides the basic run-time target software needed to support any dsp application. hardware development tools: extended development system (xds ? ) emulator (supports c6000 ? dsp multiprocessor system debug) evm (evaluation module) for a complete listing of development-support tools for the tms320c6000 ? dsp platform, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. code composer studio, dsp/bios, and xds are trademarks of texas instruments. device support 72 april 2004 ? revised january 2006 sprs247f 3.12 device support 3.12.1 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all dsp devices and support tools. each dsp commercial family member has one of three prefixes: tmx, tmp, or tms (e.g., tms 320c6412gdk600). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx / tmdx) through fully qualified production devices/tools (tms / tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device?s electrical specifications. tmp final silicon die that conforms to the device?s electrical specifications but has not completed quality and reliability verification. tms fully qualified production device. support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development-support product. tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: ?developmental product is intended for internal evaluation purposes.? tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti?s standard warranty applies. predictions show that prototype devices ( tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, gts), the temperature range (for example, ?a? is the extended temperature range), and the device speed range in megahertz (for example, -500 is 500 mhz). figure 3?7 provides a legend for reading the complete device name for any tms320c6000 ? dsp platform member. the zts package, like the gts package, is a 288-ball plastic bga only with pb-free balls. for device part numbers and further ordering information for tms320c6413/c6410 in the gts and zts package types, see the ti website (http://www.ti.com) or contact your ti sales representative. device support 73 april 2004 ? revised january 2006 sprs247f c64x dsp: 6413 6410 prefix device speed range tms 320 c6413 gts 500 tmx = experimental device tmp = prototype device tms = qualified device smx= experimental device, mil smj = mil-prf-38535, qml sm = high rel (non-38535) device family 320 = tms320 dsp family package type ? gts = 288-pin plastic bga zts = 288-pin plastic bga, with pb-free soldered balls device ? ? the extended temperature ?a version? devices may have different operating conditions than the commercial temperature devices. for more details, see the recommended operating conditions portion of this data sheet. ? bga = ball grid array the zts mechanical package designator represents the version of the gts package with pb-free balls. for more detailed information, see the mechanical data section of this document. ? for actual device part numbers (p/ns) and ordering information, see the ti website (www.ti.com). temperature range (default: 0 c to 90 c) ? ( a ) blank = 0 c to 90 c, commercial temperature a = ?40 c to 105 c, extended temperature 500 (500-mhz cpu, 100-mhz emif) [c6413] 400 (400-mhz cpu, 100-mhz emif) [c6410] figure 3?7. tms320c6413/c6410 dsp device nomenclature for additional information, see the tms320c6413, tms320c6410 digital signal processors silicon errata (literature number sprz219) device support 74 april 2004 ? revised january 2006 sprs247f 3.12.2 documentation support extensive documentation supports all tms320 ? dsp family generations of devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; complete user?s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. the following is a brief, descriptive list of support documentation specific to the c6000 ? dsp devices: the tms320c6000 cpu and instruction set reference guide (literature number spru189) describes the c6000 ? dsp cpu (core) architecture, instruction set, pipeline, and associated interrupts. the tms320c6000 dsp peripherals overview reference guide (literature number spru190) provides an overview and briefly describes the functionality of the peripherals available on the c6000 ? dsp platform of devices. this document also includes a table listing the peripherals available on the c6000 devices along with literature numbers and hyperlinks to the associated peripheral documents. the tms320c64x technical overview (literature number spru395) gives an introduction to the c64x ? digital signal processor, and discusses the application areas that are enhanced by the c64x ? dsp velociti.2 ? vliw architecture. the tms320c6000 dsp multichannel audio serial port (mcasp) reference guide (literature number spru041) describes the functionality of the mcasp peripheral. tms320c6000 dsp inter-integrated circuit (i2c) module reference guide (literature number spru175) describes the functionality of the i2c peripherals available on the c6413/c6410 device except for the additional interrupt and new gpio capability. for more detailed information on the additional interrupt and gpio capability, see the i2c section of this data manual and the tms320c6410/c6413 dsp inter-integrated circuit (i2c) module reference guide (literature number sprz221). the tms320c6413, tms320c6410 digital signal processors silicon errata (literature number sprz219) describes the known exceptions to the functional specifications for particular silicon revisions of the tms320c6413 and tms320c6410 devices. the using ibis models for t iming analysis application report (literature number spra839) describes how to properly use ibis models to attain accurate timing analysis for a given system. the tools support documentation is electronically available within the code composer studio ? integrated development environment (ide). for a complete listing of c6000 ? dsp latest documentation, visit the t exas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). tms320 is a trademark of texas instruments. peripherals detailed description (device-specific) 75 april 2004 ? revised january 2006 sprs247f 4 peripherals detailed description (device-specific) 4.1 clock pll and oscillator most of the internal c64x ? dsp clocks are generated from a single source through the clkin pin. this source clock either drives the pll, which multiplies the source clock frequency to generate the internal cpu clock, or bypasses the pll to become the internal cpu clock. to use the pll to generate the cpu clock, the external pll filter circuit must be properly designed. figure 4?1 shows the external pll circuitry for either x1 (pll bypass) or other pll multiply modes. to minimize the clock jitter, a single clean power supply should power both the c64x ? dsp device and the external clock oscillator circuit. the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see the input and output clocks electricals section. rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the dsp requirements in this data sheet (see the electrical characteristics over recommended ranges of supply voltage and operating case temperature table and the input and output clocks electricals section). clock pll and oscillator 76 april 2004 ? revised january 2006 sprs247f pllmult 1 0 pllclk clkmode0 clkmode1 c2 c1 emi filter 3.3 v /2 /8 /4 /6 00 01 10 cpu clock peripheral bus, edma clock timer internal clock clkout4, peripheral clock clkout6 /2 /4 emif 00 01 10 ek2rate (gblctl.[19,18]) eclkout2 eclkout1 pll x5, x6?x12, x16, x18?x22, x24 10 f 0.1 f aea[20:19] (for the pll options, clkmode pins setup, and pll clock frequency ranges, see table 4?1 and table 4?2.) internal to c6413/10 pllv aeclkin clkmode2 clkmode3 clkin oscv ss ? oscout oscv dd ? oscin 470 pf 470 pf osc. ? clkinsel 1 0 c6 c5 c7 ? c8 ? r s ? r b ? ? ? exact values for these components depend on choice of crystal. for recommended crystal and component values, see table 4?3. ? do not connect any of these nodes to board power or ground if the oscillator is used. they are internally connected for proper operation. if clkin is being used instead of the oscillator, then oscv dd and oscv ss may either be left open, or oscv dd may be tied to cv dd and oscv ss may be tied to ground. auxclk for mcasps osc_dis notes: a. place all pll external components (c1, c2, and the emi filter) as close to the c6000 ? dsp device as possible. for the best performance, ti recommends that all the pll external components be on a single side of the board without jumpers, switches, or components other than the ones shown. b. for reduced pll jitter, maximize the spacing between switching signals and the pll external components (c1, c2, and the emi filter). c. the 3.3-v supply for the emi filter must be from the same 3.3-v power plane supplying the i/o voltage, dv dd . d. emi filter manufacturer tdk part number acf451832-333, -223, -153, -103. panasonic part number exccet103u. e. if clkin is used instead of oscin, tie oscin to ground to minimize noise and current. (do not leave oscin floating.) figure 4?1. external pll circuitry for either pll multiply modes or x1 (bypass) mode clock pll and oscillator 77 april 2004 ? revised january 2006 sprs247f for proper c6413/c6410 device operation, the clkinsel pin must be used in conjunction with the osc_dis pin. the osc_dis pin must follow the clkinsel pin operation. for more details on these two configuration pins, see the device configuration at device reset section of this data sheet. table 4?1. tms320c6413 pll multiply factor options, clock frequency ranges, and typical lock time for ?500 devices ? gts and zts packages ? 23 x 23 mm bga clkmode[3:0] clkmode (pll multiply factors) clkin range (mhz) cpu clock frequency range (mhz) oscin range (mhz) cpu clock frequency range (mhz) typical lock time ( s) ? 0 0 0 0 bypass (x1) 12?100 12?100 12?30 12?30 n/a 0 0 0 1 x5 28?100 140?500 28?30 140?150 0 0 1 0 x6 23?83 140?500 23?30 140?180 0 0 1 1 x7 20?71 140?500 20?30 140?210 0 1 0 0 x8 17?63 140?500 17?30 140?240 0 1 0 1 x9 15?56 140?500 15?30 140?270 0 1 1 0 x10 14?50 140?500 14?30 140?300 0 1 1 1 x11 12?45 140?500 12?30 140?330 1 0 0 0 x12 12?42 144?500 12?30 144?360 75 1 0 0 1 x16 12?31 192?500 12?30 192?480 75 1 0 1 0 x18 12?28 216?500 12?28 216?500 1 0 1 1 x19 12?26 228?500 12?26 228?500 1 1 0 0 x20 12?25 240?500 12?25 240?500 1 1 0 1 x21 12?24 252?500 12?24 252?500 1 1 1 0 x22 12?23 264?500 12?23 264?500 1 1 1 1 x24 12?21 288?500 12?21 288?500 ? use external pullup resistors on the clkmode pins (clkmode1 and clkmode0) to set the c6413/c6410 device to one of the valid pll multiply clock modes (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24). with internal pulldown resistor s on the clkmode pins (clkmode3, clkmode2, clkmode1, clkmode0), the default clock mode is x1 (bypass). ? under some operating conditions, the maximum pll lock time may vary by as much as 150% from the specified typical value. for ex ample, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s. clock pll and oscillator 78 april 2004 ? revised january 2006 sprs247f table 4?2. tms320c6410 pll multiply factor options, clock frequency ranges, and typical lock time for ?400 devices ? gts and zts packages ? 23 x 23 mm bga clkmode[3:0] clkmode (pll multiply factors) clkin range (mhz) cpu clock frequency range (mhz) oscin range (mhz) cpu clock frequency range (mhz) typical lock time ( s) ? 0 0 0 0 bypass (x1) 12?100 12?100 12?30 12?30 n/a 0 0 0 1 x5 28?80 140?400 28?30 140?150 0 0 1 0 x6 23?67 140?400 23?30 140?180 0 0 1 1 x7 20?57 140?400 20?30 140?210 0 1 0 0 x8 17?50 140?400 17?30 140?240 0 1 0 1 x9 15?44 140?400 15?30 140?270 0 1 1 0 x10 14?40 140?400 14?30 140?300 0 1 1 1 x11 12?36 140?400 12?30 140?330 1 0 0 0 x12 12?33 144?400 12?30 144?360 75 1 0 0 1 x16 12?25 192?400 12?25 192?400 75 1 0 1 0 x18 12?22 216?400 12?22 216?400 1 0 1 1 x19 12?21 228?400 12?21 228?400 1 1 0 0 x20 12?20 240?400 12?20 240?400 1 1 0 1 x21 12?19 252?400 12?19 252?400 1 1 1 0 x22 12?18 264?400 12?18 264?400 1 1 1 1 x24 12?17 288?400 12?17 288?400 ? use external pullup resistors on the clkmode pins (clkmode1 and clkmode0) to set the c6413/c6410 device to one of the valid pll multiply clock modes (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24). with internal pulldown resistor s on the clkmode pins (clkmode3, clkmode2, clkmode1, clkmode0), the default clock mode is x1 (bypass). ? under some operating conditions, the maximum pll lock time may vary by as much as 150% from the specified typical value. for ex ample, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s. for the lowest jitter on the oscillator circuit, it is recommended that a pair of 470-pf capacitors be connected between isolated (not directly connected to the board supply) oscv dd and oscv ss pins. this helps to cancel out switching noise from other circuits on the dsp device. table 4?3 shows a recommended crystal and tank circuit values for the c6413/c6410 pll circuitry. table 4?3. crystal and tank circuit recommendations components recommended part numbers or values manufacturer 24.576 mhz 1as245766aha (smd-49) crystal 24.576 mhz 1af245766aaa (at-49) kds ? diashinku corp. crystal 22.5792 mhz 1as225796ag (smd-49) kds ? diashinku corp. 22.5792 mhz 1af225796a (at-49) r b 1 m ? ? r s 0 ? ? c7 c8 8 pf ? host-port interface (hpi) peripheral 79 april 2004 ? revised january 2006 sprs247f 4.2 host-port interface (hpi) peripheral the tms320c6413/c6410 device includes a user-configurable 16-bit or 32-bit host-port interface (hpi16/hpi32). on the c6413/c6410 device the hpi peripheral pins are muxed with the mcasp1 and gp0 peripheral pins. by default, the hpi peripheral pin functions are enabled. for more detailed information on the c6413/c6410 device pin muxing, see the device configurations section of this data sheet. the hpi peripheral can be disabled or enabled at reset through the hpi enable function of the t out0/hpi_en pin. the hpi is enabled when the tout0/hpi_en pin is sampled low at reset and it is disabled if the pin is sample high at reset. the tout0/hpi_en pin has an internal pulldown that enables the hpi by default. however, the hpi can be disabled via an external pullup resistor or by having an external device such as an fpga/cpld drive that pin high at reset. in the latter case, the external device should ensure it has stopped driving this pin to avoid contention. the hpi enable function can only be set a reset and cannot be changed via software. the hd5 pin controls the hpi_width, allowing the user to configure the hpi as a 16-bit or 32-bit peripheral. for more details on hpi peripheral configuration and the associated pins, see the device configurations section of this data sheet. multichannel audio serial port (mcasp) peripheral 80 april 2004 ? revised january 2006 sprs247f 4.3 multichannel audio serial port (mcasp) peripheral the tms320c6413/c6410 device includes two multichannel audio serial port (mcasp) interface peripheral (mcasp0 and mcasp1). on the c6413/c6410 device the mcasp1 peripheral pins are muxed with the hpi peripheral pins. by default, the hpi peripheral pin functions are enabled. for the c6413/c6410 device mcasp1 is a standalone peripheral, not muxed. for more detailed information on the c6413/c6410 device pin muxing, see the device configurations section of this data sheet. the mcasp is a serial port optimized for the needs of multichannel audio applications. the mcasp consists of a transmit and receive section. these sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. the mcasp module also includes a pool of 16 shift registers that may be configured to operate as either transmit data, receive data, or general-purpose i/o (gpio). the transmit section of the mcasp can transmit data in either a time-division-multiplexed (tdm) synchronous serial format or in a digital audio interface (dit) format where the bit stream is encoded for s/pdif, aes-3, iec-60958, cp-430 transmission. the receive section of the mcasp supports the tdm synchronous serial format. the mcasp can support one transmit data format (either a tdm format or dit format) and one receive format at a time. all transmit shift registers use the same format and all receive shift registers use the same format. however, the transmit and receive formats need not be the same. both the transmit and receive sections of the mcasp also support burst mode which is useful for non-audio data (for example, passing control information between two dsps). the mcasp peripheral has additional capability for flexible clock generation, and error detection/handling, as well as error management. for more detailed information on and the functionality of the mcasp peripheral, see the tms320c6000 dsp multichannel audio serial port (mcasp) reference guide (literature number spru041). 4.3.1 mcasp block diagram figure 4?2 illustrates the major blocks along with external signals of the tms320c6413/c6410 mcasp peripheral; and shows the 6 serial data [axrx] pins. the mcasp also includes full general-purpose i/o (gpio) control, so any pins not needed for serial transfers can be used for general-purpose i/o. multichannel audio serial port (mcasp) peripheral 81 april 2004 ? revised january 2006 sprs247f receive clock generator ahclkrx aclkrx ? clock check transmit generator clock transmit aclkxx ahclkxx dit ram transmit generator frame sync afsxx detect error receive frame sync generator formatter transmit data amutex amuteinx afsrx ? serializer 0 serializer 1 serializer 3 serializer 2 serializer 6 serializer 7 serializer 5 serializer 4 (high- frequency) receive clock check (high- frequency) receive formatter data mcaspx dma transmit dma receive individually programmable tx/rx/gpio control gpio axrx[0] axrx[1] axrx[3] axrx[2] axrx[5] axrx[4] ? on the c6413/c6410 device, the mcasp1 peripheral has some additional pins muxed with afsr1 and with aclkr1 pins (i.e., afsr1[1], afsr1[2], afsr1[3] and aclkr1[1]. aclkr1[2], aclkr1[3], respectively). ? on the c6413/c6410 device, the mcasp0 peripheral is standalone, not muxed and the mcasp1 peripheral is muxed with the hpi peripheral. for more detailed information on multiplexed pins, see the device configurations section of this data sheet. figure 4?2. mcasp0 and mcasp1 ? configuration i2c 82 april 2004 ? revised january 2006 sprs247f 4.4 i2c the tms320c6413/c6410 device includes two i2c peripheral modules (i2c0 and i2c1). note: when using the i2c modules (any mode), ensure there are external pullup resistors on the sdax and sclx pins. one of the i2c modules on the tms320c6413/c6410 may be used by the dsp to control local peripherals ics (dacs, adcs, etc.) while the other module may be used to communicate with other controllers in a system or to implement a user interface. the i2cx port supports: ? compatible with philips i2c specification revision 2.1 (january 2000) ? fast mode up to 400 kbps (no fail-safe i/o buffers) ? noise filter to remove noise 50 ns or less ? 7- and 10-bit device addressing modes ? multi-master (transmit/receive) and slave (transmit/receive) functionality ? events: dma, interrupt, or polling ? slew-rate limited open-drain output buffers ? general-purpose input and output (gpio) functionality for i2c pins for more detailed information on c6413/6410 i2c additional features, such as gpio capability, etc., see the tms320c6000 dsp inter?integrated circuit (i2c) module reference guide (literature number spru175) and the tms320c6410/c6413/c6418 dsp inter?integrated circuit (i2c) module reference guide (literature number sprz221) addendum. general-purpose input/output (gpio) 83 april 2004 ? revised january 2006 sprs247f figure 4?3 is a block diagram of the i2c0 and i2c1 modules. clock prescale i2cpscx peripheral clock (cpu/4) i2cclkhx generator bit clock i2cclklx noise filter scl i2cxsrx i2cdxrx transmit transmit shift transmit buffer i2cdrrx shift i2crsrx receive buffer receive receive filter sda i2c data noise i2coarx i2csarx slave address control address own i2cmdrx i2ccntx mode data count source interrupt interrupt status i2cisrcx i2cstrx enable interrupt i2cierx interrupt/dma i2cx module note a: shading denotes control/status registers. i2c clock i2cemdrx i2cpfuncx i2cpdirx i2cpdinx i2cpdoutx i2cpdsetx i2cpdclrx gpio control function pin direction pin in pin data out pin data set pin data clear pin data extended mode figure 4?3. i2cx module block diagram 4.5 general-purpose input/output (gpio) on the c6413/c6410 device the gpio peripheral pins gp0[15:9] are muxed with the hpi peripheral pins hd[15:9], respectively. by default, the hpi peripheral pin functions are enabled [t out0/hpi_en pin internall pulled low]. for more detailed information on device/peripheral configuration and the c6413/c6410 device pin muxing, see the device configurations section of this data sheet. to use the gp0[15:0] software-configurable gpio pins, the gpxen bits in the gp enable (gpen) register and the gpxdir bits in the gp direction (gpdir) register must be properly configured. gpxen = 1 gp[x] pin is enabled gpxdir = 0 gp[x] pin is an input gpxdir = 1 gp[x] pin is an output where ?x? represents one of the 15 through 0 gpio pins figure 4?4 shows the gpio enable bits in the gpen register for the c6413/c6410 device. to use any of the gpx pins as general-purpose input/output functions, the corresponding gpxen bit must be set to ?1? (enabled). default values are device-specific, so refer to figure 4?4 for the c6413/c6410 default configuration. general-purpose input/output (gpio) 84 april 2004 ? revised january 2006 sprs247f 31 24 23 16 reserved r-0 15 14 13 12 11 10 9 8 7 6543 210 gp15 en gp14 en gp13 en gp12 en gp11 en gp10 en gp9 en gp8 en gp7 en gp6 en gp5 en gp4 en gp3 en gp2 en gp1 en gp0 en r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 legend: r/w = readable/w riteable; - n = value after reset, -x = undefined value after reset figure 4?4. gpio enable register (gpen) [hex address: 01b0 0000] general-purpose input/output (gpio) 85 april 2004 ? revised january 2006 sprs247f figure 4?5 shows the gpio direction bits in the gpdir register. this register determines if a given gpio pin is an input or an output providing the corresponding gpxen bit is enabled (set to ?1?) in the gpen register. by default, all the gpio pins are configured as input pins. 31 24 23 16 reserved r-0 15 14 13 12 11 10 98 7 6 5 43 2 10 gp15 dir gp14 dir gp13 dir gp12 dir gp11 dir gp10 dir gp9 dir gp8 dir gp7 dir gp6 dir gp5 dir gp4 dir gp3 dir gp2 dir gp1 dir gp0 dir r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r/w = readable/w riteable; - n = value after reset, -x = undefined value after reset figure 4?5. gpio direction register (gpdir) [hex address: 01b0 0004] for more detailed information on general-purpose inputs/outputs (gpios), see the tms320c6000 dsp general-purpose input/output (gpio) reference guide (literature number spru584). power-down modes logic 86 april 2004 ? revised january 2006 sprs247f 4.6 power-down modes logic figure 4?6 shows the power-down mode logic on the c6413/c6410. pwrd internal clock tree cpu ifr ier csr pd1 pd2 power- down logic clock pll clkin reset clkout6 pd3 internal peripherals clkout4 clock and dividers distribution ? external input clocks, with the exception of clkin, are not gated by the power-down mode logic. tms320c6413/c6410 figure 4?6. power-down mode logic ? note: to further save power, the percfg register can be used to disable unused peripherals. for more detailed information on disabling peripherals using the percfg register, see the device configurations section of this data sheet. 4.6.1 triggering, wake-up, and effects the power-down modes and their wake-up methods are programmed by setting the pwrd field (bits 15?10) of the control status register (csr). the pwrd field of the csr is shown in figure 4?7 and described in table 4?4. when writing to the csr, all bits of the pwrd field should be set at the same time. logic 0 should be used when writing to the reserved bit (bit 15) of the pwrd field. the csr is discussed in detail in the tms320c6000 cpu and instruction set reference guide (literature number spru189). power-down modes logic 87 april 2004 ? revised january 2006 sprs247f 31 16 15 14 13 12 11 10 9 8 reserved enable or non-enabled interrupt wake enabled interrupt wake pd3 pd2 pd1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 0 legend: r/w?x = read/write reset value note: the shadowed bits are not part of the power-down logic discussion and therefore are not covered here. for information on t hese other bit fields in the csr register, see the tms320c6000 cpu and instruction set reference guide (literature number spru189). figure 4?7. pwrd field of the csr register a delay of up to nine clock cycles may occur after the instruction that sets the pwrd bits in the csr before the pd mode takes effect. as best practice, nops should be padded after the pwrd bits are set in the csr to account for this delay. if pd1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where pd1 took effect. if pd1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruct ion where pd1 took effect. in the case with an enabled interrupt, the gie bit in the csr and the nmie bit in the interrupt enable register (ier) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where pd1 took effect upon pd1 mode termination by an enabled interrupt. pd2 and pd3 modes can only be aborted by device reset. table 4?4 summarizes all the power-down modes. power-supply sequencing 88 april 2004 ? revised january 2006 sprs247f table 4?4. characteristics of the power-down modes prwd field (bits 15?10) power-down mode wake-up method effect on chip?s operation 000000 no power-down ? ? 001001 pd1 wake by an enabled interrupt cpu halted (except for the interrupt logic) power-down mode blocks the internal clock inputs at the 010001 pd1 wake by an enabled or non-enabled interrupt power-down mode blocks the internal clock inputs at the boundary of the cpu, preventing most of the cpu?s logic from switching. during pd1, edma transactions can proceed between peripherals and internal memory. 011010 pd2 ? wake by a device reset output clock from pll is halted, stopping the internal clock structure from switching and resulting in the entire chip being halted. all register and internal ram contents are preserved. all functional i/o ?freeze? in the last state when the pll clock is turned off. 011100 pd3 ? wake by a device reset input clock to the pll stops generating clocks. all register and internal ram contents are preserv ed. all functional i/o ?freeze? in the last state when the pll clock is turned off. following reset, the pll needs time to re-lock, just as it does following power-up. wake-up from pd3 takes longer than wake-up from pd2 because the pll needs to be re-locked, just as it does following power-up. all others reserved ? ? ? when entering pd2 and pd3, all functional i/o remains in the previous state. however, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. under these con ditions, peripherals will not operate according to specifications. 4.6.2 c64x power-down mode with an emulator if user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow the emulator access to the system. this condition prevails until the emulator is reset or the cable is removed from the header. if power measurements are to be performed when in a power-down mode, the emulator cable should be removed. when the dsp is in power-down mode pd2 or pd3, emulation logic will force any emulation execution command (such as step or run) to spin in idle. for this reason, pc writes (such as loading code) will fail. a dsp reset will be required to get the dsp out of pd2/pd3. 4.7 power-supply sequencing ti dsps do not require specific power sequencing between the core supply and the i/o supply. however, systems should be designed to ensure that neither supply is powered up for extended periods of time ( > 1 second) if the other supply is below the proper operating voltage. 4.7.1 power-supply design considerations a dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and i/o power up. a schottky diode can also be used to tie the core rail to the i/o rail (see figure 4?8). power-supply sequencing 89 april 2004 ? revised january 2006 sprs247f dv dd cv dd v ss c6000 dsp schottky diode i/o supply core supply gnd figure 4?8. schottky diode diagram core and i/o supply voltage regulators should be located close to the dsp (or dsp array) to minimize inductance and resistance in the power delivery path. additionally, when designing for high-performance applications utilizing the c6000 ? platform of dsps, the pc board should include separate power planes for core, i/o, and ground, all bypassed with high-quality low-esl/esr capacitors. ti dsps do not require specific power sequencing between the core supply and the i/o supply. however, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. 4.8 power-supply decoupling in order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the dsp. assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supply and 30 for the i/o supply. these caps need to be close to the dsp power pins, no more than 1.25 cm maximum distance to be ef fective. physically smaller caps, such as 0402, are better because of their lower parasitic inductance. proper capacitance values are also important. small bypass caps (near 560 pf) should be closest to the power pins. medium bypass caps (220 nf or as large as can be obtained in a small package) should be next closest. ti recommends no less than 8 small and 8 medium caps per supply (32 total) be placed immediately next to the bga vias, using the ?interior? bga space and at least the corners of the ?exterior?. eight larger caps (4 for each supply) can be placed further away for bulk decoupling. large bulk caps (on the order of 100 f) should be furthest away (but still as close as possible). no less than 4 large caps per supply (8 total) should be placed outside of the bga. any cap selection needs to be evaluated from a yield/manufacturing po int-of-view. as with the selection of any component, verification of capacitor availability over the product?s production lifetime should be considered. peripheral power-down operation 90 april 2004 ? revised january 2006 sprs247f 4.9 peripheral power-down operation the c6413/c6410 device can be powered down in two ways: ? power-down due to software configuration ? relates to the default state of the peripheral configuration bits in the percfg register. ? power-down during run-time via software configuration on the c6413/c6410 device, the hpi, mcasp1, and gp0 peripherals pin muxing is controlled (selected) at the pin level during chip reset (e.g., hpi_en and hd5 pins). if mcasp1 pin muxing is selected, then the mcasp1en bit in the peripheral configuration register (percfg.8) must be configured properly to enable the mcasp1 peripheral. the mcasp1, mcasp0, i2c1, and i2c0 peripheral functions are selected via the peripheral configuration (percfg) register bits. for more detailed information on the peripheral configuration pins and the percfg register bits, see the device configurations section of this document. ieee 1149.1 jtag compatibility statement 91 april 2004 ? revised january 2006 sprs247f 4.10 ieee 1149.1 jtag compatibility statement the tms320c6413/c6410 dsp requires that both trst and reset be asserted upon power up to be properly initialized. while reset initializes the dsp core, trst initializes the dsp?s emulation logic. both resets are required for proper operation. note: trst is synchronous and must be clocked by tclk; otherwise, bscan may not respond as expected after trst is asserted. while both trst and reset need to be asserted upon power up, only reset needs to be released for the dsp to boot properly. trst may be asserted indefinitely for normal operation, keeping the jtag port interface and dsp?s emulation logic in the reset state. trst only needs to be released when it is necessary to use a jtag controller to debug the dsp or exercise the dsp?s boundary scan functionality. reset must be released in order for boundary-scan jtag to read the variant field of idcode correctly. other boundary-scan instructions work correctly independent of current state of reset . the tms320c6413/6410 dsp includes an internal pulldown (ipd) on the trst pin to ensure that trst will always be asserted upon power up and the dsp?s internal emulation logic will always be properly initialized when this pin is not routed out. jtag controllers from texas instruments actively drive trst high. however, some third-party jtag controllers may not drive trst high but expect the use of an external pullup resistor on trst . when using this type of jtag controller, assert trst to initialize the dsp after powerup and externally drive trst high before attempting any emulation or boundary scan operations. following the release of reset , the low-to-high transition of trst must occur to latch the state of emu1 and emu0. the emu[1:0] pins configure the device for either boundary scan mode or normal/emulation mode. for more detailed information, see the terminal functions section of this data sheet. note: the design_warning section of the tms320c6413/c6410 bsdl file contains information and constraints regarding proper device operation while in boundary scan mode. for more detailed information on the c6413/c6410 jtag emulation, see the tms320c6000 dsp designing for jtag emulation reference guide (literature number spru641). 4.11 emif device speed the rated emif speed of these devices only applies to the sdram interface when in a system that meets the following requirements: ? 1 chip-enable (ce) space (maximum of 2 chips) of sdram connected to emif ? up to 1 ce space of buffers connected to emif ? emif trace lengths between 1 and 3 inches ? 143-mhz sdram for 100-mhz operation other configurations may be possible, but timing analysis must be done to verify all ac timings are met. verification of ac timings is mandatory when using configurations other than those specified above. ti recommends utilizing i/o buffer information specification (ibis) to analyze all ac timings. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839). to maintain signal integrity, serial termination resistors should be inserted into all emif output signal lines (see the terminal functions table for the emif output signals). for more detailed information on the c6413/c6410 emif peripheral, see the tms320c6000 dsp external memory interface (emif) reference guide (literature number spru266). bootmode 92 april 2004 ? revised january 2006 sprs247f 4.12 bootmode the c6413/c6410 device resets using the active-low signal reset . while reset is low, the device is held in reset and is initialized to the prescribed reset state. refer to reset timing for reset timing characteristics and states of device pins during reset. the release of reset starts the processor running with the prescribed device configuration and boot mode. the c6413/c6410 has three types of boot modes: ? host boot if host boot is selected, upon release of reset , the cpu is internally ?stalled? while the remainder of the device is released. during this period, an external host can initialize the cpu?s memory space as necessary through the host interface, including internal configuration registers, such as those that control the emif or other peripherals. for the c6413/c6410 device, the hpi peripheral is used for host boot providing the tout0/hpi_en pin is low, enabling the hpi peripheral [default]. once the host is finished with all necessary initialization, it must set the dspint bit in the hpic register to complete the boot process. this transition causes the boot configuration logic to bring the cpu out of the ?stalled? state. the cpu then begins execution from address 0. the dspint condition is not latched by the cpu, because it occurs while the cpu is still internally ?stalled?. also, dspint brings the cpu out of the ?stalled? state only if the host boot process is selected. all memory may be written to and read by the host. this allows for the host to verify what it sends to the dsp if required. after the cpu is out of the ?stalled? state, the cpu needs to clear the dspint, otherwise, no more dspints can be received. ? emif boot (using default rom timings) upon the release of reset , the 1k-byte rom code located in the beginning of ce1 is copied to address 0 by the edma using the default rom timings, while the cpu is internally ?stalled?. the data should be stored in the endian format that the system is using. in this case, the emif automatically assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. the transfer is automatically done by the edma as a single-frame block transfer from the rom to address 0. after completion of the block transfer, the cpu is released from the ?stalled? state and starts running from address 0. ? no boot with no boot, the cpu begins direct execution from the memory located at address 0. note: operation is undefined if invalid code is located at address 0. 4.13 reset a hardware reset (reset ) is required to place the dsp into a known good state out of power-up. the reset signal can be asserted (pulled low) prior to ramping the core and i/o voltages or after the core and i/o voltages have reached their proper operating conditions. as a best practice, reset should be held low during power-up. prior to deasserting reset (low-to-high transition), the core and i/o voltages should be at their proper operating conditions and clkin should also be running at the correct frequency. device electrical specifications 93 april 2004 ? revised january 2006 sprs247f 5 device electrical specifications 5.1 absolute maximum ratings over operating case temperature range (unless otherwise noted) ? supply voltage ranges: cv dd (see note 1) ? 0.3 v to 1.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dv dd (see note 1) ?0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range: v i ?0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range: v o ?0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating case temperature range, t c : (default) 0 c to 90 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a version) [gtsa and ztsa] ?40 c to 105 c . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package temperature cycling: temperature range ?40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . number of cycles (gts, gtsa) 1000 . . . . . . . . . . . . . . . . . . . . . . . . . . number of cycles (zts, ztsa) 500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . 5.2 recommended operating conditions min nom max unit cv dd supply voltage, core (-400, -500 device) ? 1.14 1.2 1.26 v dv dd supply voltage, i/o 3.14 3.3 3.46 v v ss supply ground 0 0 0 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v v os maximum voltage during overshoot 4.3 v v us minimum voltage during undershoot ?1.0 v t c operating case temperature commercial temperature devices (gts and zts) 0 90 c t c operating case temperature extended temperature devices (gtsa and ztsa) ?40 105 c ? future variants of the c64x dsps may operate at voltages ranging from 0.9 v to 1.4 v to provide a range of system power/performance op tions. ti highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 v, 1.25 v, 1. 3 v, 1.35 v, 1.4 v with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications . examples of such supplies include the pt4660, pt5500, pt5520, pt6440, and pt6930 series from power trends, a subsidiary of texas instrum ents. not incorporating a flexible supply may limit the system?s ability to easily adapt to future versions of c64x devices. the absolute maximum ratings should not be exceeded for more than 30% of the cycle period. device electrical specifications 94 april 2004 ? revised january 2006 sprs247f 5.3 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) parameter test conditions ? min typ max unit v oh high-level output voltage dv dd = min, i oh = max 2.4 v v ol low-level output voltage dv dd = min, i ol = max 0.4 v v i = v ss to dv dd no opposing internal resistor 10 ua i i input current v i = v ss to dv dd opposing internal pullup resistor ? 50 100 150 ua v i = v ss to dv dd opposing internal pulldown resistor ? ?150 ?100 ?50 ua i oh high-level output current emif, clkout4, clkout6, emux ?16 ma i oh high-level output current timer, tdo, gpio, mcbsp, hpi ?8 ma emif, clkout4, clkout6, emux 16 ma i ol low-level output current timer, tdo, gpio, mcbsp, hpi 8 ma i ol low-level output current scl1, sda1, scl0, and sda0 3 ma i oz off-state output current v o = dv dd or 0 v 10 ua i cdd core supply current cv dd = 1.2 v, cpu clock = 500 mhz 568 ma i cdd core supply current cv dd = 1.2 v, cpu clock = 400 mhz 465 ma i ddd i/o supply current dv dd = 3.3 v, cpu clock = 500 mhz 140 ma i ddd i/o supply current dv dd = 3.3 v, cpu clock = 400 mhz 132 ma c i input capacitance 10 pf c o output capacitance 10 pf ? for test conditions shown as min, max, or nom, use the appropriate value specified in the recommended operating conditions tabl e. ? applies only to pins with an internal pullup (ipu) or pulldown (ipd) resistor. measured with average activity (50% high/50% low power) at 25 c case temperature and 100-mhz emif for -500 and -400 speeds. this model represents a device performing high-dsp-activity operations 50% of the time, and the remainder performing low-dsp-activity oper ations. the high/low-dsp-activity models are defined as follows: high-dsp-activity model: cpu: 8 instructions/cycle with 2 lddw instructions [l1 data memory: 128 bits/cycle via lddw instructions; l1 program memory: 256 bits/cycle; l2/emif edma: 50% writes, 50% reads to/from sdram (50% bit-switching)] mcbsp: 2 channels at e1 rate timers: 2 timers at maximum rate low-dsp-activity model: cpu: 2 instructions/cycle with 1 ldh instruction [l1 data memory: 16 bits/cycle; l1 program memory: 256 bits per 4 cycles; l2/emif edma: none] mcbsp: 2 channels at e1 rate timers: 2 timers at maximum rate the actual current draw is highly application-dependent. for more details on core and i/o activity, refer to the tms320c6410/13 power consumption summary application report (literature number spraa59). 5.4 recommended clock and control signal transition behavior all clocks and control signals must transition between v ih and v il (or between v il and v ih ) in a monotonic manner. device electrical specifications 95 april 2004 ? revised january 2006 sprs247f 6 parameter information transmission line 4.0 pf 1.85 pf z0 = 50 ? (see note) tester pin electronics data sheet timing reference point output under test note: the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmiss ion line effects must be taken into account. a transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line eff ect. the transmission line is intended as a load only. it is not necessary to add or subtract the transmission line delay (2 ns or l onger) from the data sheet timings. 42 ? 3.5 nh device pin (see note) input requirements in this data sheet are tested with an input slew rate of < 4 volts per nanosecond (4 v/ns) at the device pin . figure 6?1. test load circuit for ac timing measurements the load capacitance value stated is only for characterization and measurement of ac timing signals. this load capacitance value does not indicate the maximum load the device is capable of driving. 6.1 signal transition levels all input and output timing parameters are referenced to 1.5 v for both ?0? and ?1? logic levels. v ref = 1.5 v figure 6?2. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks. v ref = v il max (or v ol max) v ref = v ih min (or v oh min) figure 6?3. rise and fall transition time voltage reference levels 6.2 signal transition rates all timings are tested with an input edge rate of 4 volts per nanosecond (4 v/ns). device electrical specifications 96 april 2004 ? revised january 2006 sprs247f parameter measurement information (continued) 6.3 ac transient rise/fall time specifications figure 6?4 and figure 6?5 show the ac transient specifications for rise and fall time. for device-specific information on these values, refer to the recommended operating conditions section of this data sheet. v os (max) v ih (min) minimum risetime waveform valid region t = 0.3 t c (max) ? ground figure 6?4. ac transient specification rise time ? t c = the peripheral cycle time. t = 0.3 t c (max) ? v il (max) ground v us (max) ? t c = the peripheral cycle time. figure 6?5. ac transient specification fall time 6.4 timing parameters and board routing analysis the timing parameter values specified in this data sheet do not include delays by board routings. as a good board design practice, such delays must always be taken into account. timing values may be adjusted by increasing/decreasing such delays. ti recommends utilizing the available i/o buf fer information specification (ibis) models to analyze the timing characteristics correctly. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spr a839). if needed, external logic har dware such as buf fers may be used to compensate any timing differences. for inputs, timing is most impacted by the round-trip propagation delay from the dsp to the external device and from the external device to the dsp. this round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see table 6?1 and figure 6?6). device electrical specifications 97 april 2004 ? revised january 2006 sprs247f figure 6?6 represents a general transfer between the dsp and an external device. the figure also represents board route delays and how they are perceived by the dsp and the external device. table 6?1. board-level timing example (see figure 6?6) no. description 1 clock route delay 2 minimum dsp hold time 3 minimum dsp setup time 4 external device hold time requirement 5 external device setup time requirement 6 control signal route delay 7 external device hold time 8 external device access time 9 dsp hold time requirement 10 dsp setup time requirement 11 data route delay 1 2 3 4 5 6 7 8 10 11 eclkoutx (output from dsp) eclkoutx (input to external device) control signals ? (output from dsp) control signals (input to external device) data signals ? (output from external device) data signals ? (input to dsp) 9 ? control signals include data for writes. ?data signals are generated during reads from an external device. figure 6?6. board-level input/output timings peripheral electrical specifications 98 april 2004 ? revised january 2006 sprs247f 7 peripheral electrical specifications 7.1 input and output clocks table 7?1. timing requirements for external crystal oscillator input (oscin and oscout) no. ?400 ?500 unit no. min max unit 1 f osc input oscillator frequency 12 30 mhz ? the pll multiplier factors (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x24) further limit the min and max valu es for clkin and oscin. for more details on these limitations, see table 4?1 and table 4?2 of the clock pll and oscillator section of this data sheet. table 7?2. timing requirements for clkin ?? (see figure 7?1) no. ?400 ?500 unit no . pll mult mode x1 (bypass) unit min max min max 1 t c(clkin) cycle time, clkin 10 ? 83.3 10 ? 83.3 ns 2 t w(clkinh) pulse duration, clkin high 0.45c 0.45c ns 3 t w(clkinl) pulse duration, clkin low 0.45c 0.45c ns 4 t t(clkin) transition time, clkin 5 1 ns 5 t j(clkin) period jitter, clkin 0.02c 0.02c ns ? the pll multiplier factors (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x24) further limit the min and max valu es for clkin and oscin. for more details on these limitations, see table 4?1 and table 4?2 of the clock pll and oscillator section of this data sheet. ? the reference points for the rise and fall transitions are measured at v il max and v ih min. c = clkin cycle time in ns. for example, when clkin frequency is 50 mhz, use c = 20 ns. clkin 2 3 4 4 5 1 figure 7?1. clkin timing input and output clocks 99 april 2004 ? revised january 2006 sprs247f table 7?3. switching characteristics over recommended operating conditions for clkout4 ?? (see figure 7?2) no. parameter ?400 ?500 unit no. parameter min max unit 1 t c(cko4) cycle time, clkout4 4p ? 0.7 4p + 0.7 ns 2 t w(cko4h) pulse duration, clkout4 high 2p ? 0.7 2p + 0.7 ns 3 t w(cko4l) pulse duration, clkout4 low 2p ? 0.7 2p + 0.7 ns 4 t t(cko4) transition time, clkout4 1 ns ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. ? ph is the high period of clkin in ns and pl is the low period of clkin in ns. p = 1/cpu clock frequency in nanoseconds (ns) clkout4 3 4 4 2 1 figure 7?2. clkout4 timing table 7?4. switching characteristics over recommended operating conditions for clkout6 ?? (see figure 7?3) no. parameter ?400 ?500 unit no. parameter min max unit 1 t c(cko6) cycle time, clkout6 6p ? 0.7 6p + 0.7 ns 2 t w(cko6h) pulse duration, clkout6 high 3p ? 0.7 3p + 0.7 ns 3 t w(cko6l) pulse duration, clkout6 low 3p ? 0.7 3p + 0.7 ns 4 t t(cko6) transition time, clkout6 1 ns ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. ? ph is the high period of clkin in ns and pl is the low period of clkin in ns. p = 1/cpu clock frequency in nanoseconds (ns) clkout6 3 4 4 2 1 figure 7?3. clkout6 timing input and output clocks 100 april 2004 ? revised january 2006 sprs247f table 7?5. timing requirements for aeclkin for emifa ?? (see figure 7?4) no. ?400 ?500 unit no. min max unit 1 t c(eki) cycle time, aeclkin 6 ? 16p ns 2 t w(ekih) pulse duration, aeclkin high 2.7 ns 3 t w(ekil) pulse duration, aeclkin low 2.7 ns 4 t t(eki) transition time, aeclkin 3 ns 5 t j(eki) period jitter, aeclkin 0.02e ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? the reference points for the rise and fall transitions are measured at v il max and v ih min. e = the emif input clock (aeclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa. ? minimum aeclkin cycle times must be met, even when aeclkin is generated by an internal clock source. minimum aeclkin times are based on internal logic speed; the maximum useable speed of the emif may be lower due to ac timing requirements. 100-mhz operation is achievable if the requirements of the emif device speed section are met. aeclkin 2 3 4 4 5 1 figure 7?4. aeclkin timing for emifa table 7?6. switching characteristics over recommended operating conditions for aeclkout1 for the emifa module #|| (see figure 7?5) no. parameter ?400 ?500 unit no. parameter min max unit 1 t c(eko1) cycle time, aeclkout1 e ? 0.7 e + 0.7 ns 2 t w(eko1h) pulse duration, aeclkout1 high eh ? 0.7 eh + 0.7 ns 3 t w(eko1l) pulse duration, aeclkout1 low el ? 0.7 el + 0.7 ns 4 t t(eko1) transition time, aeclkout1 1 ns 5 t d(ekih-eko1h) delay time, aeclkin high to aeclkout1 high 1 8 ns 6 t d(ekil-eko1l) delay time, aeclkin low to aeclkout1 low 1 8 ns e = the emif input clock (aeclkin, cpu/4 clock, or cpu/6 clock) period in ns. # the reference points for the rise and fall transitions are measured at v ol max and v oh min. || eh is the high period of e (emif input clock period) in ns and el is the low period of e (emif input clock period) in ns for em ifa. 5 6 2 3 aeclkin aeclkout1 4 4 1 figure 7?5. aeclkout1 timing for the emifa module input and output clocks 101 april 2004 ? revised january 2006 sprs247f table 7?7. switching characteristics over recommended operating conditions for aeclkout2 for the emifa module ?? (see figure 7?6) no. parameter ?400 ?500 unit no. parameter min max unit 1 t c(eko2) cycle time, aeclkout2 ne ? 0.7 ne + 0.7 ns 2 t w(eko2h) pulse duration, aeclkout2 high 0.5ne ? 0.7 0.5ne + 0.7 ns 3 t w(eko2l) pulse duration, aeclkout2 low 0.5ne ? 0.7 0.5ne + 0.7 ns 4 t t(eko2) transition time, aeclkout2 1 ns 5 t d(ekih-eko2h) delay time, eclkin high to aeclkout2 high 1 8 ns 6 t d(ekil-eko2l) delay time, eclkin low to aeclkout2 low 1 8 ns ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. ? e = the emif input clock (aeclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa. n = the emif input clock divider; n = 1, 2, or 4. 5 6 aeclkin aeclkout2 3 2 4 4 1 figure 7?6. aeclkout2 timing for the emifa module asynchronous memory timing 102 april 2004 ? revised january 2006 sprs247f 7.2 asynchronous memory timing table 7?8. timing requirements for asynchronous memory cycles for emifa module ?? (see figure 7?7 and figure 7?8) no. ?400 ?500 unit no. min max unit 3 t su(edv-areh) setup time, aedx valid before aare high 6.5 ns 4 t h(areh-edv) hold time, aedx valid after aare high 1 ns 6 t su(ardy-eko1h) setup time, aardy valid before aeclkoutx high 3 ns 7 t h(eko1h-ardy) hold time, aardy valid after aeclkoutx high 3 ns ? to ensure data setup time, simply program the strobe width wide enough. ardy is internally synchronized. the ardy signal is rec ognized in the cycle for which the setup and hold time is met. the ardy signal is only recognized two cycles before the end of the programmed strobe time and while ardy is low, the strobe time is extended cycle-by-cycle. when ardy is recognized low, the end of the strobe time is t wo cycles after ardy is recognized high to use ardy as an asynchronous input, the pulse width of the ardy signal should be wide enough (e.g., p ulse width = 2e) to ensure setup and hold time is met. ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. table 7?9. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifa module ?? (see figure 7?7 and figure 7?8) no. parameter ?400 ?500 unit no. parameter min max unit 1 t osu(selv-arel) output setup time, select signals valid to aare low rs * e ? 1.5 ns 2 t oh(areh-seliv) output hold time, aare high to select signals invalid rh * e ? 1.9 ns 5 t d(eko1h-arev) delay time, aeclkoutx high to aare valid 1 7 ns 8 t osu(selv-awel) output setup time, select signals valid to aawe low ws * e ? 1.7 ns 9 t oh(aweh-seliv) output hold time, aawe high to select signals invalid wh * e ? 1.8 ns 10 t d(eko1h-awev) delay time, aeclkoutx high to aawe valid 1.3 7.1 ns ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. e = eclkout1 period in ns for emifa ? select signals for emifa include: acex , abe[3.:0] , aea[22:3], aaoe; and for emifa writes, include aed[31:0]. asynchronous memory timing 103 april 2004 ? revised january 2006 sprs247f 7 7 6 6 setup = 2 strobe = 3 not ready hold = 2 be address 1 1 1 1 5 4 aardy 5 aeclkoutx acex aea[22:3] aed[31:0] aaoe /asdras /asoe ? aare /asdcas /asads /asre ? abe[3:0] aawe /asdwe /aswe ? 2 2 2 2 3 read data ? aoe /sdras /soe , are /sdcas /sads /sre , and awe /sdwe /swe operate as aoe (identified under select signals), are , and awe , respectively, during asynchronous memory accesses. figure 7?7. asynchronous memory read timing for emifa asynchronous memory timing 104 april 2004 ? revised january 2006 sprs247f setup = 2 strobe = 3 not ready hold = 2 be address write data 10 10 8 8 8 8 7 7 6 6 aeclkoutx acex aea[22:3] aed[31:0] abe[3:0] aardy aaoe /asdras /asoe ? aare /asdcas /asads /asre ? aawe /asdwe /aswe ? 9 9 9 9 ? aoe /sdras /soe , are /sdcas /sads /sre , and awe /sdwe /swe operate as aoe (identified under select signals), are , and awe , respectively, during asynchronous memory accesses. figure 7?8. asynchronous memory write timing for emifa programmable synchronous interface timing 105 april 2004 ? revised january 2006 sprs247f 7.3 programmable synchronous interface timing table 7?10. timing requirements for programmable synchronous interface cycles for emifa module (see figure 7?9) no. ?400 ?500 unit no. min max unit 6 t su(edv-ekoxh) setup time, read aedx valid before aeclkoutx high 3.1 ns 7 t h(ekoxh-edv) hold time, read aedx valid after aeclkoutx high 1.5 ns table 7?11. switching characteristics over recommended operating conditions for programmable synchronous interface cycles for emifa module ? (see figure 7?9?figure 7?11) no. parameter ?400 ?500 unit no. parameter min max unit 1 t d(ekoxh-cev) delay time, aeclkoutx high to acex valid 1.3 6.4 ns 2 t d(ekoxh-bev) delay time, aeclkoutx high to abex valid 6.4 ns 3 t d(ekoxh-beiv) delay time, aeclkoutx high to abex invalid 1.3 ns 4 t d(ekoxh-eav) delay time, aeclkoutx high to aeax valid 6.4 ns 5 t d(ekoxh-eaiv) delay time, aeclkoutx high to aeax invalid 1.3 ns 8 t d(ekoxh-adsv) delay time, aeclkoutx high to asads /asre valid 1.3 6.4 ns 9 t d(ekoxh-oev) delay time, aeclkoutx high to, asoe valid 1.3 6.4 ns 10 t d(ekoxh-edv) delay time, aeclkoutx high to aedx valid 6.4 ns 11 t d(ekoxh-ediv) delay time, aeclkoutx high to aedx invalid 1.3 ns 12 t d(ekoxh-wev) delay time, aeclkoutx high to aswe valid 1.3 6.4 ns ? the following parameters are programmable via the emif ce space secondary control register (cexsec): ? read latency (syncrl): 0-, 1-, 2-, or 3-cycle read latency ? write latency (syncwl): 0-, 1-, 2-, or 3-cycle write latency ? acex assertion length (ceext): for standard sbsram or zbt sram interface, acex goes inactive after the final command has been issued (ceext = 0). for synchronous fifo interface with glue, acex is active when asoe is active (ceext = 1). ? function of asads /asre (renen): for standard sbsram or zbt sram interface, asads /asre acts as asads with deselect cycles (renen = 0). for fifo interface, asads /asre acts as asre with no deselect cycles (renen = 1). ? synchronization clock (sncclk): synchronized to aeclkout1 or aeclkout2 programmable synchronous interface timing 106 april 2004 ? revised january 2006 sprs247f aeclkoutx acex abe[3:0] aea[22:3] aed[31:0] aare /asdcas /asads / asre aaoe /asdras /asoe aawe /asdwe /aswe be1 be2 be3 be4 q1 q2 q3 q4 9 1 4 5 8 9 6 7 3 1 2 be1 be2 be3 be4 ea1 ea2 ea4 8 read latency = 2 ea3 ? the read latency and the length of cex assertion are programmable via the syncrl and ceext fields, respectively, in the emifa ce space secondary control register (cexsec). in this figure, syncrl = 2 and ceext = 0. ? the following parameters are programmable via the emif ce space secondary control register (cexsec): ? read latency (syncrl): 0-, 1-, 2-, or 3-cycle read latency ? write latency (syncwl): 0-, 1-, 2-, or 3-cycle write latency ? acex assertion length (ceext): for standard sbsram or zbt sram interface, acex goes inactive after the final command has been issued (ceext = 0). for synchronous fifo interface with glue, acex is active when asoe is active (ceext = 1). ? function of asads /asre (renen): for standard sbsram or zbt sram interface, asads /asre acts as asads with deselect cycles (renen = 0). for fifo interface, asads /asre acts as asre with no deselect cycles (renen = 1). ? synchronization clock (sncclk): synchronized to aeclkout1 or aeclkout2 aare /asdcas /asads /asre , aaoe /asdras /asoe , and aawe /asdwe /aswe operate as asads /asre , asoe , and aswe , respectively, during programmable synchronous interface accesses. figure 7?9. programmable synchronous interface read timing for emifa (with read latency = 2) ?? programmable synchronous interface timing 107 april 2004 ? revised january 2006 sprs247f aeclkoutx acex abe[3:0] aea[22:3] aed[31:0] aare /asdcas /asads /asre aaoe /asdras /asoe aawe /asdwe /aswe be1 be2 be3 be4 q1 q2 q3 q4 12 11 3 1 12 10 4 2 1 8 5 8 ea1 ea2 ea3 ea4 10 ? the write latency and the length of acex assertion are programmable via the syncwl and ceext fields, respectively, in the emifa ce space secondary control register (cexsec). in this figure, syncwl = 0 and ceext = 0. ? the following parameters are programmable via the emif ce space secondary control register (cexsec): ? read latency (syncrl): 0-, 1-, 2-, or 3-cycle read latency ? write latency (syncwl): 0-, 1-, 2-, or 3-cycle write latency ? acex assertion length (ceext): for standard sbsram or zbt sram interface, acex goes inactive after the final command has been issued (ceext = 0). for synchronous fifo interface with glue, acex is active when asoe is active (ceext = 1). ? function of asads /asre (renen): for standard sbsram or zbt sram interface, asads /asre acts as asads with deselect cycles (renen = 0). for fifo interface, asads /asre acts as asre with no deselect cycles (renen = 1). ? synchronization clock (sncclk): synchronized to aeclkout1 or aeclkout2 aare /asdcas /asads /asre , aaoe /asdras /asoe , and aawe /asdwe /aswe operate as asads /asre , asoe , and aswe , respectively, during programmable synchronous interface accesses. figure 7?10. programmable synchronous interface write timing for emifa (with write latency = 0) ?? programmable synchronous interface timing 108 april 2004 ? revised january 2006 sprs247f aeclkoutx acex abe[3:0] aea[22:3] aed[31:0] aare /asdcas /asads / asre aaoe /asdras /asoe aawe /asdwe /aswe be1 be2 be3 be4 q1 q2 q3 11 3 12 10 4 2 1 8 5 8 ea1 ea2 ea3 ea4 10 write latency = 1 ? 1 q4 12 ? the write latency and the length of acex assertion are programmable via the syncwl and ceext fields, respectively, in the emifa ce space secondary control register (cexsec). in this figure, syncwl = 1 and ceext = 0. ? the following parameters are programmable via the emif ce space secondary control register (cexsec): ? read latency (syncrl): 0-, 1-, 2-, or 3-cycle read latency ? write latency (syncwl): 0-, 1-, 2-, or 3-cycle write latency ? acex assertion length (ceext): for standard sbsram or zbt sram interface, acex goes inactive after the final command has been issued (ceext = 0). for synchronous fifo interface with glue, acex is active when asoe is active (ceext = 1). ? function of asads /asre (renen): for standard sbsram or zbt sram interface, asads /asre acts as asads with deselect cycles (renen = 0). for fifo interface, asads /asre acts as asre with no deselect cycles (renen = 1). ? synchronization clock (sncclk): synchronized to eclkout1 or eclkout2 aare /asdcas /asads /asre , aaoe /asdras /asoe , and aawe /asdwe /aswe operate as asads /asre , asoe , and aswe , respectively, during programmable synchronous interface accesses. figure 7?11. programmable synchronous interface write timing for emifa (with write latency = 1) ?? synchronous dram timing 109 april 2004 ? revised january 2006 sprs247f 7.4 synchronous dram timing table 7?12. timing requirements for synchronous dram cycles for emifa module (see figure 7?12) no. ?400 ?500 unit no. min max unit 6 t su(edv-eko1h) setup time, read aedx valid before aeclkoutx high 2.1 ns 7 t h(eko1h-edv) hold time, read aedx valid after aeclkoutx high 2.5 ns table 7?13. switching characteristics over recommended operating conditions for synchronous dram cycles for emifa module (see figure 7?12?figure 7?19) no. parameter ?400 ?500 unit no. parameter min max unit 1 t d(eko1h-cev) delay time, aeclkoutx high to acex valid 1.3 6.4 ns 2 t d(eko1h-bev) delay time, aeclkoutx high to abex valid 6.4 ns 3 t d(eko1h-beiv) delay time, aeclkoutx high to abex invalid 1.3 ns 4 t d(eko1h-eav) delay time, aeclkoutx high to aeax valid 6.4 ns 5 t d(eko1h-eaiv) delay time, aeclkoutx high to aeax invalid 1.3 ns 8 t d(eko1h-casv) delay time, aeclkoutx high to asdcas valid 1.3 6.4 ns 9 t d(eko1h-edv) delay time, aeclkoutx high to aedx valid 6.4 ns 10 t d(eko1h-ediv) delay time, aeclkoutx high to aedx invalid 1.3 ns 11 t d(eko1h-wev) delay time, aeclkoutx high to asdwe valid 1.3 6.4 ns 12 t d(eko1h-ras) delay time, aeclkoutx high to asdras valid 1.3 6.4 ns 13 t d(eko1h-ackev) delay time, aeclkoutx high to asdcke valid 1.3 6.4 ns 14 t d(eko1h-pdtv) delay time, aeclkoutx high to pdt valid 1.3 6.4 ns synchronous dram timing 110 april 2004 ? revised january 2006 sprs247f aeclkoutx acex abe[3:0] aea[12:3] aed[31:0] aea13 aaoe /asdras /asoe ? aare /asdcas /asads / asre ? aawe /asdwe /aswe ? aea[22:14] be1 be2 be3 be4 bank column d1 d2 d3 d4 8 7 6 5 5 5 1 3 2 8 4 4 4 1 read pdt ? 14 14 ? aare /asdcas /asads /asre , aawe /asdwe /aswe , and aaoe /asdras /asoe operate as asdcas , asdwe , and asdras , respectively, during sdram accesses. ? pdt signal is only asserted when the edma is in pdt mode (set the pdts bit to 1 in the edma options parameter ram). for pdt read, data is not latched into emif. the pdtrl field in the pdt control register (pdtctl) configures the latency of the pdt signal with respect to the data phase of a read transaction. the latency of the pdt signal for a read can be programmed to 0, 1, 2, or 3 by setting pdtrl to 00, 01, 10, or 11, respectively. pdtrl equals 00 (zero latency) in figure 7?12. figure 7?12. sdram read command (cas latency 3) for emifa synchronous dram timing 111 april 2004 ? revised january 2006 sprs247f aeclkoutx acex abe[3:0] aea[12:3] aed[31:0] aaoe /asdras /asoe ? aare /asdcas /asads / asre ? aawe /asdwe /aswe ? aea13 aea[22:14] be1 be2 be3 be4 bank column d1 d2 d3 d4 11 8 9 5 5 5 4 2 11 8 9 4 4 2 1 10 3 4 write pdt ? 14 14 ? aare /asdcas /asads /asre , aawe /asdwe /aswe , and aaoe /asdras /asoe operate as asdcas , asdwe , and asdras , respectively, during sdram accesses. ? pdt signal is only asserted when the edma is in pdt mode (set the pdtd bit to 1 in the edma options parameter ram). for pdt write, data is not driven (in high-z). the pdtwl field in the pdt control register (pdtctl) configures the latency of the pdt signal with respect to the data phase of a write transaction. the latency of the pdt signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting pdtwl to 00, 01, 10, or 11, respectively. pdtwl equals 00 (zero latency) in figure 7?13. figure 7?13. sdram write command for emifa synchronous dram timing 112 april 2004 ? revised january 2006 sprs247f aeclkoutx acex abe[3:0] aea[22:14] aed[31:0] aea13 aaoe /asdras /asoe ? aare /asdcas /asads / asre ? aawe /asdwe /aswe ? bank activate row address row address 12 5 5 5 1 aea[12:3] actv 12 4 4 4 1 ? aare /asdcas /asads /asre , aawe /asdwe /aswe , and aaoe /asdras /asoe operate as asdcas , asdwe , and asdras , respectively, during sdram accesses. figure 7?14. sdram actv command for emifa aeclkoutx acex abe[3:0] aea[22:14, 12:3] aed[31:0] aea13 aaoe /asdras /asoe ? aare /asdcas /asads / asre ? aawe /asdwe /aswe ? 11 12 5 1 dcab 11 12 4 1 ? aare /asdcas /asads /asre , aawe /asdwe /aswe , and aaoe /asdras /asoe operate as asdcas , asdwe , and asdras , respectively, during sdram accesses. figure 7?15. sdram dcab command for emifa synchronous dram timing 113 april 2004 ? revised january 2006 sprs247f aeclkoutx acex abe[7:0] aea[22:14] aed[31:0] aea13 aaoe /asdras /asoe ? aare /asdcas /asads / asre ? aawe /asdwe /aswe ? aea[12:3] bank 11 12 5 5 1 deac 11 12 4 4 1 ? aare /asdcas /asads /asre , aawe /asdwe /aswe , and aaoe /asdras /asoe operate as asdcas , asdwe , and asdras , respectively, during sdram accesses. figure 7?16. sdram deac command for emifa aeclkoutx acex abe[3:0] aea[22:14, 12:3] aed[31:0]] aea13 aaoe /asdras /asoe ? aare /asdcas /asads / asre ? aawe /asdwe /aswe ? 8 12 1 refr 8 12 1 ? aare /asdcas /asads /asre , aawe /asdwe /aswe , and aaoe /asdras /asoe operate as asdcas , asdwe , and asdras , respectively, during sdram accesses. figure 7?17. sdram refr command for emifa synchronous dram timing 114 april 2004 ? revised january 2006 sprs247f aeclkoutx acex abe[3:0] aea[22:3] aed[31:0] aaoe /asdras / asoe ? aare /asdcas /asads / asre ? aawe /asdwe /aswe ? mrs value 11 8 12 5 1 mrs 11 8 12 4 1 ? aare /asdcas /asads /asre , aawe /asdwe /aswe , and aaoe /asdras /asoe operate as asdcas , asdwe , and asdras , respectively, during sdram accesses. figure 7?18. sdram mrs command for emifa end self-refresh self refresh 13 13 aeclkoutx acex abe[3:0] aea[22:14, 12:3] aea13 aed[31:0] aaoe /asdras /asoe ? aawe /asdwe /aswe ? asdcke tras cycles aa re /asdcas /asads /asre ? ? aare /asdcas /asads /asre , aawe /asdwe /aswe , and aaoe /asdras /asoe operate as asdcas , asdwe , and asdras , respectively, during sdram accesses. figure 7?19. sdram self-refresh timing for emifa hold /holda timing 115 april 2004 ? revised january 2006 sprs247f 7.5 hold /holda timing table 7?14. timing requirements for the hold /holda cycles for emifa module ? (see figure 7?20) no. ?400 ?500 unit no. min max unit 3 t h(holdal-holdl) hold time, hold low after holda low e ns ? e = the emif input clock (eclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa. table 7?15. switching characteristics over recommended operating conditions for the hold /holda cycles for emifa module ?? (see figure 7?20) no. parameter ?400 ?500 unit no. parameter min max unit 1 t d(holdl-emhz) delay time, hold low to emifa bus high impedance 2e ? ns 2 t d(emhz-holdal) delay time, emif bus high impedance to holda low 0 2e ns 4 t d(holdh-emlz) delay time, hold high to emif bus low impedance 2e 7e ns 5 t d(emlz-holdah) delay time, emifa bus low impedance to holda high 0 2e ns 6 t d(holdl-ekohz) delay time, hold low to aeclkoutx high impedance 2e ? ns 7 t d(holdh-ekolz) delay time, hold high to aeclkoutx low impedance 2e 7e ns ? e = the emif input clock (eclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa. ? emifa bus consists of: ace[3:0] , abe[3:0] , aed[31:0], aea[22:3], aare /asdcas /asads /asre , aaoe /asdras /asoe , and aawe /asdwe /aswe , asdcke, asoe3 , and apdt . the ekxhz bits in the emif global control register (gblctl) determine the state of the eclkoutx signals during holda . if ekxhz = 0, eclkoutx continues clocking during hold mode. if ekxhz = 1, eclkoutx goes to high impedance during hold mode, as shown in figure 7?20. ? all pending emif transactions are allowed to complete before holda is asserted. if no bus transactions are occurring, then the minimum delay time can be achieved. also, bus hold can be indefinitely delayed by setting nohold = 1. hold holda emif bus ? dsp owns bus external requestor owns bus dsp owns bus c6413/c6410 c6413/c6410 1 3 25 4 aeclkoutx ? (ekxhz = 0) aeclkoutx ? (ekxhz = 1) 6 7 ? emifa bus consists of: ace[3:0] , abe[3:0] , aed[31:0], aea[22:3], aare /asdcas /asads /asre , aaoe /asdras /asoe , and aawe /asdwe /aswe , asdcke, asoe3 , and apdt . ? the ekxhz bits in the emif global control register (gblctl) determine the state of the eclkoutx signals during holda . if ekxhz = 0, eclkoutx continues clocking during hold mode. if ekxhz = 1, eclkoutx goes to high impedance during hold mode, as shown in figure 7?20. figure 7?20. hold /holda timing for emifa busreq timing 116 april 2004 ? revised january 2006 sprs247f 7.6 busreq timing table 7?16. switching characteristics over recommended operating conditions for the busreq cycles for emifa module (see figure 7?21) no. parameter ?400 ?500 unit no. parameter min max unit 1 t d(aeko1h-abusrv) delay time, aeclkoutx high to abusreq valid 0.6 7.1 ns aeclkoutx 1 abusreq 1 figure 7?21. busreq timing for emifa 7.7 reset timing note: if a configuration pin must be routed out from the device, the internal pullup/pulldown (ipu/ipd) resistor should not be relied upon. ti recommends the use of an external pullup/pulldown resistor. table 7?17. timing requirements for reset (see figure 7?22) no. ?400 ?500 unit no. min max unit 1 t w(rst) width of the reset pulse ? 250 s 16 t su(boot) setup time, boot configuration bits valid before reset high ? 4e or 4c ? ns 17 t h(boot) hold time, boot configuration bits valid after reset high ? 4p ns ? aea[22:19], lendian, bootmode[1:0], and aeclkin_sel[1:0] are the boot configuration pins during device reset. ? e = 1/eclkin clock frequency in ns. c = 1/clkin clock frequency in ns. select the min parameter value, whichever value is larger. p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? the device must be reset after the oscillator has stabilized. if resetz is low during power-up, it can be kept low until the os cillator has stabilized. note: a device reset does not affect the state of the oscillator. reset timing 117 april 2004 ? revised january 2006 sprs247f table 7?18. switching characteristics over recommended operating conditions during reset # (see figure 7?22) no. parameter ?400, ?500 unit no. parameter min max unit 2 t d(rstl-ecki) delay time, reset low to eclkin synchronized internally 2e 3p + 20e ns 3 t d(rsth-ecki) delay time, reset high to eclkin synchronized internally 2e 8p + 20e ns 4 t d(rstl-ecko1hz) delay time, reset low to eclkout1 high impedance 2e ns 5 t d(rsth-ecko1v) delay time, reset high to eclkout1 valid 8p + 20e ns 6 t d(rstl-emifzhz) delay time, reset low to emif z high impedance 2e 3p + 4e ns 7 t d(rsth-emifzv) delay time, reset high to emif z valid 16e 8p + 20e ns 8 t d(rstl-emifhiv) delay time, reset low to emif high group invalid 2e ns 9 t d(rsth-emifhv) delay time, reset high to emif high group valid 8p + 20e ns 10 t d(rstl-emifliv) delay time, reset low to emif low group invalid 2e ns 11 t d(rsth-emiflv) delay time, reset high to emif low group valid 8p + 20e ns 12 t d(rstl-highiv) delay time, reset low to high group invalid 0 ns 13 t d(rsth-highv) delay time, reset high to high group valid 11p ns 14 t d(rstl-zhz) delay time, reset low to z group high impedance 0 ns 15 t d(rsth-zv) delay time, reset high to z group valid 2p 8p ns 18 t d(oscstart) delay time, internal oscillator startup time ||? clkinsel = 0 41032 x oscin ns p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? the device must be reset after the oscillator has stabilized. if resetz is low during power-up, it can be kept low until the os cillator has stabilized. note: a device reset does not affect the state of the oscillator. # e = the emif input clock (eclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa. || assuming core power supply has stabilized at recommended operating conditions. emif z group consists of: aea[22:3], aed[31:0], ace[3:0] , abe[3:0] , aare /asdcas /asads /asre ,aawe /asdwe /aswe , and aaoe /asdras /asoe , asoe3 , asdcke, apdt ., and aeclkout1 emif high group consists of: aholda (when the corresponding hold input is high) emif low group consists of: abusreq; aholda (when the corresponding hold input is low) high group consists of: hrdy (when hpi is enabled, otherwise in z group) z group consists of: clkx0, clkx1, fsx0, fsx1, dx0, dx1, clks0, clks1, dr0, dr1, clkr0, clkr1, fsr0, fsr1, tout0/hpi_en , tout1/lendian, gp0[7:0], hd[7:0], hd[15:8]/gp0[15:8], hd[21:16]/axr1[5:0], hd22/afsx1, hd23/afsr1, hd24/aclkx1, hd25/aclkr1, hd26/ahclkr1, hd27/ahclkx1, hd28/amute1, hd29/amutein1, hd30, hd31, hrdy , hds2 , hds1 /aclkr1[3], hcs /aclkr1[2], has /aclkr1[1], hr/w /afsr1[3], hhwil/afsr1[2] (16-bit hpi mode only), hcntl0/afsr1[1], hcntl1, hint ,, aclkr0, afsr0, ahclkr0, amutein0, amute0, axr0[5:0], sda1, scl1, sda0, scl0, tdo, and emu[11:0] reset timing 118 april 2004 ? revised january 2006 sprs247f aeclkout2 17 14 1 clkout4 clkout6 reset aeclkin high group ? z group ?? boot and device configuration inputs 16 15 3 2 10 8 emif z group ?? emif high group ? emif low group ? 11 9 7 6 13 12 aeclkout1 5 4 ? emif z group consists of: aea[22:3], aed[31:0], ace[3:0] , abe[3:0] , aare /asdcas /asads /asre ,aawe /asdwe /aswe , and aaoe /asdras /asoe , asoe3 , asdcke, apdt ., and aeclkout1 emif high group consists of: aholda (when the corresponding hold input is high) emif low group consists of: abusreq; aholda (when the corresponding hold input is low) high group consists of: hrdy (when hpi is enabled, otherwise in z group) z group consists of: clkx0, clkx1, fsx0, fsx1, dx0, dx1, clks0, clks1, dr0, dr1, clkr0, clkr1, fsr0, fsr1, tout0/hpi_en , tout1/lendian, gp0[7:0], hd[7:0], hd[15:8]/gp0[15:8], hd[21:16]/axr1[5:0], hd22/afsx1, hd23/afsr1, hd24/aclkx1, hd25/aclkr1, hd26/ahclkr1, hd27/ahclkx1, hd28/amute1, hd29/amutein1, hd30, hd31, hrdy , hds2 , hds1 /aclkr1[3], hcs /aclkr1[2], has /aclkr1[1], hr/w /afsr1[3], hhwil/afsr1[2] (16-bit hpi mode only), hcntl0/afsr1[1], hcntl1, hint ,, aclkr0, afsr0, ahclkr0, amutein0, amute0, axr0[5:0], sda1, scl1, sda0, scl0, tdo, and emu[11:0] ? if aea[22:19], lendian, bootmode[1:0], and aeclkin_sel[1:0] pins are actively driven, care must be taken to ensure no timing co ntention between parameters 6, 7, 14, 15, 16, and 17. boot and device configurations inputs (during reset) include: aea[22:19], lendian, bootmode[1:0], and aeclkin_sel[1:0]. figure 7?22. reset timing ? external interrupt timing 119 april 2004 ? revised january 2006 sprs247f 7.8 external interrupt timing table 7?19. timing requirements for external interrupts ? (see figure 7?23) no. ?400 ?500 unit no. min max unit 1 t w(ilow) width of the nmi interrupt pulse low 4p ns 1 t w(ilow) width of the ext_int interrupt pulse low 8p ns 2 t w(ihigh) width of the nmi interrupt pulse high 4p ns 2 t w(ihigh) width of the ext_int interrupt pulse high 8p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. 2 1 ext_intx, nmi figure 7?23. external/nmi interrupt timing 7.9 multichannel audio serial port (mcasp) timing table 7?20. timing requirements for mcasp (see figure 7?24 and figure 7?25) no. ?400 ?500 unit no. min max unit 1 t c(ahckrx) cycle time, ahclkr/x 20 ns 2 t w(ahckrx) pulse duration, ahclkr/x high or low 10 ns 3 t c(ckrx) cycle time, aclkr/x aclkr/x ext 25 ns 4 t w(ckrx) pulse duration, aclkr/x high or low aclkr/x ext 12.25 ns 5 t su(frxc-krx) setup time, afsr/x input valid before aclkr/x latches data aclkr/x int 5 ns 5 t su(frxc-krx) setup time, afsr/x input valid before aclkr/x latches data aclkr/x ext 5 ns 6 t h(ckrx-frx) hold time, afsr/x input valid after aclkr/x latches data aclkr/x int 5 ns 6 t h(ckrx-frx) hold time, afsr/x input valid after aclkr/x latches data aclkr/x ext 5 ns 7 t su(axr-ckrx) setup time, axr input valid before aclkr/x latches data aclkr/x int 5 ns 7 t su(axr-ckrx) setup time, axr input valid before aclkr/x latches data aclkr/x ext 5 ns 8 t h(ckrx-axr) hold time, axr input valid after aclkr/x latches data aclkr/x int 5 ns 8 t h(ckrx-axr) hold time, axr input valid after aclkr/x latches data aclkr/x ext 5 ns multichannel audio serial port (mcasp) timing 120 april 2004 ? revised january 2006 sprs247f table 7?21. switching characteristics over recommended operating conditions for mcasp (see figure 7?26 and figure 7?27) no. parameter ?400 ?500 unit no. parameter min max unit 9 t c(ahckrx) cycle time, ahclkr/x 20 ns 10 t w(ahckrx) pulse duration, ahclkr/x high or low 10 ns 11 t c(ckrx) cycle time, aclkr/x aclkr/x int 33 ns 12 t w(ckrx) pulse duration, aclkr/x high or low aclkr/x int 16.5 ns 13 t d(ckrx-frx) delay time, aclkr/x transmit edge to afsx/r output valid aclkr/x int ?1 5 ns 13 t d(ckrx-frx) delay time, aclkr/x transmit edge to afsx/r output valid aclkr/x ext 2 12 ns 14 t d(ckrx-axrv) delay time, aclkr/x transmit edge to axr output valid aclkr/x int ?1 5 ns 14 t d(ckrx-axrv) delay time, aclkr/x transmit edge to axr output valid aclkr/x ext 2 12 ns 15 t dis(ckrx?axrhz) disable time, axr high impedance following last data bit from aclkr/x int 0 10 ns 15 t dis(ckrx?axrhz) disable time, axr high impedance following last data bit from aclkr/x transmit edge aclkr/x ext 0 10 ns multichannel audio serial port (mcasp) timing 121 april 2004 ? revised january 2006 sprs247f multichannel audio serial port (mcasp) timing (continued) 8 7 4 4 3 2 2 1 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay) afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay) afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data in/receive) 6 5 aclkr/x (clkrp = clkxp = 0) ? aclkr/x (clkrp = clkxp = 1) ? ? for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is config ured for falling edge (to shift data in). ? for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is confi gured for rising edge (to shift data in). figure 7?28. mcasp input timings multichannel audio serial port (mcasp) timing 122 april 2004 ? revised january 2006 sprs247f multichannel audio serial port (mcasp) timing (continued) 15 14 13 13 13 13 13 13 13 12 12 11 10 10 9 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay) afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay) afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data out/transmit) aclkr/x (clkrp = clkxp = 0) ? aclkr/x (clkrp = clkxp = 1) ? ? for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is confi gured for rising edge (to shift data in). ? for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is config ured for falling edge (to shift data in). figure 7?29. mcasp output timings inter-integrated circuits (i2c) timing 123 april 2004 ? revised january 2006 sprs247f 7.10 inter-integrated circuits (i2c) timing table 7?22. timing requirements for i2c timings ? (see figure 7?30) ?400 ?500 no. standard mode fast mode unit min max min max 1 t c(scl) cycle time, scl 10 2.5 s 2 t su(sclh-sdal) setup time, scl high before sda low (for a repeated start condition) 4.7 0.6 s 3 t h(scll-sdal) hold time, scl low after sda low (for a start and a repeated start condition) 4 0.6 s 4 t w(scll) pulse duration, scl low 4.7 1.3 s 5 t w(sclh) pulse duration, scl high 4 0.6 s 6 t su(sdav-sdlh) setup time, sda valid before scl high 250 100 ? ns 7 t h(sda-sdll) hold time, sda valid after scl low (for i 2 c bus ? devices) 0 0 0.9 ? s 8 t w(sdah) pulse duration, sda high between stop and start conditions 4.7 1.3 s 9 t r(sda) rise time, sda 1000 20 + 0.1c b # 300 ns 10 t r(scl) rise time, scl 1000 20 + 0.1c b # 300 ns 11 t f(sda) fall time, sda 300 20 + 0.1c b # 300 ns 12 t f(scl) fall time, scl 300 20 + 0.1c b # 300 ns 13 t su(sclh-sdah) setup time, scl high before sda high (for stop condition) 4 0.6 s 14 t w(sp) pulse duration, spike (must be suppressed) 0 50 ns 15 c b # capacitive load for each bus line 400 400 pf ? the i2c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is pow ered down. ? a fast-mode i 2 c-bus ? device can be used in a standard-mode i 2 c-bus ? system, but the requirement t su(sda?sclh) 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch t he low period of the scl signal, it must output the next data bit to the sda line t r max + t su(sda?sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. ? the maximum t h(sda?scll) has only to be met if the device does not stretch the low period [t w(scll) ] of the scl signal. # c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. 10 8 4 3 7 12 5 6 14 2 3 13 stop start repeated start stop sda scl 1 11 9 figure 7?30. i2c receive timings inter-integrated circuits (i2c) timing 124 april 2004 ? revised january 2006 sprs247f table 7?23. switching characteristics for i2c timings ? (see figure 7?31) ?400 ?500 no. parameter standard mode fast mode unit min max min max 16 t c(scl) cycle time, scl 10 2.5 s 17 t d(sclh-sdal) delay time, scl high to sda low (for a repeated start condition) 4.7 0.6 s 18 t d(sdal-scll) delay time, sda low to scl low (for a start and a repeated start condition) 4 0.6 s 19 t w(scll) pulse duration, scl low 4.7 1.3 s 20 t w(sclh) pulse duration, scl high 4 0.6 s 21 t d(sdav-sdlh) delay time, sda valid to scl high 250 100 ns 22 t v(sdll-sdav) valid time, sda valid after scl low (for i 2 c bus ? devices) 0 0 0.9 s 23 t w(sdah) pulse duration, sda high between stop and start conditions 4.7 1.3 s 24 t r(sda) rise time, sda 1000 20 + 0.1c b ? 300 ns 25 t r(scl) rise time, scl 1000 20 + 0.1c b ? 300 ns 26 t f(sda) fall time, sda 300 20 + 0.1c b ? 300 ns 27 t f(scl) fall time, scl 300 20 + 0.1c b ? 300 ns 28 t d(sclh-sdah) delay time, scl high to sda high (for stop condition) 4 0.6 s 29 c p capacitance for each i2c pin 10 10 pf ? c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. 25 23 19 18 22 27 20 21 17 18 28 stop start repeated start stop sda scl 16 26 24 figure 7?31. i2c transmit timings host-port interface (hpi) timing 125 april 2004 ? revised january 2006 sprs247f 7.11 host-port interface (hpi) timing table 7?24. timing requirements for host-port interface cycles ?? (see figure 7?32 through figure 7?39) no. ?400 ?500 unit no. min max unit 1 t su(selv-hstbl) setup time, select signals valid before hstrobe low 5 ns 2 t h(hstbl-selv) hold time, select signals valid after hstrobe low 2.4 ns 3 t w(hstbl) pulse duration, hstrobe low 4p ? ns 4 t w(hstbh) pulse duration, hstrobe high between consecutive accesses 4p ns 10 t su(selv-hasl) setup time, select signals valid before has low 5 ns 11 t h(hasl-selv) hold time, select signals valid after has low 2 ns 12 t su(hdv-hstbh) setup time, host data valid before hstrobe high 5 ns 13 t h(hstbh-hdv) hold time, host data valid after hstrobe high 2.8 ns 14 t h(hrdyl-hstbl) hold time, hstrobe low after hrdy low. hstrobe should not be inactivated until hrdy is active (low); otherwise, hpi writes will not complete properly. 2 ns 18 t su(hasl-hstbl) setup time, has low before hstrobe low 2 ns 19 t h(hstbl-hasl) hold time, has low after hstrobe low 2.1 ns ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. select signals include: hcntl[1:0] and hr/w . for hpi16 mode only, select signals also include hhwil. ? select the parameter value of 4p or 12.5 ns, whichever is larger. table 7?25. switching characteristics over recommended operating conditions during host-port interface cycles ?? (see figure 7?32 through figure 7?39) no. parameter ?400 ?500 unit no. parameter min max unit 6 t d(hstbl-hrdyh) delay time, hstrobe low to hrdy high # 1.3 4p + 8 ns 7 t d(hstbl-hdlz) delay time, hstrobe low to hd low impedance for an hpi read 2 ns 8 t d(hdv-hrdyl) delay time, hd valid to hrdy low ?3 ns 9 t oh(hstbh-hdv) output hold time, hd valid after hstrobe high 1.5 ns 15 t d(hstbh-hdhz) delay time, hstrobe high to hd high impedance 12 ns 16 t d(hstbl-hdv) delay time, hstrobe low to hd valid (hpi16 mode, 2nd half-word only) 2p + 8 or 0p + 8 || ns ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. # this parameter is used during hpid reads and writes. for reads, at the beginning of a word transfer (hpi32) or the first half-word t ransfer (hpi16) on the falling edge of hstrobe , the hpi sends the request to the edma internal address generation hardware, and hrdy remains high until the edma internal address generation hardware loads the requested data into hpid. for writes, hrdy goes high if the internal write buffer is full. || if preceeding hstrobe high pulse width > 6p, then this parameter value can be 0p + 8 ns. host-port interface (hpi) timing 126 april 2004 ? revised january 2006 sprs247f 1st half-word 2nd half-word 8 6 15 9 16 15 9 7 4 3 2 1 2 1 2 1 2 1 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (output) hrdy 3 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 7?32. hpi16 read timing (has not used, tied high) has ? hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (output) hrdy 1st half-word 2nd half-word 8 6 15 9 16 15 9 7 4 3 11 10 11 10 11 10 11 10 11 10 11 10 19 19 18 18 ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 7?33. hpi16 read timing (has used) host-port interface (hpi) timing 127 april 2004 ? revised january 2006 sprs247f 1st half-word 2nd half-word 13 12 13 12 4 14 3 2 1 2 1 2 1 2 1 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (input) hrdy 3 6 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 7?34. hpi16 write timing (has not used, tied high) 1st half-word 2nd half-word 13 12 13 12 4 14 3 11 10 11 10 11 10 11 10 11 10 11 10 has ? hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (input) hrdy 19 19 18 18 6 ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 7?35. hpi16 write timing (has used) host-port interface (hpi) timing 128 april 2004 ? revised january 2006 sprs247f 6 3 has hcntl[1:0] hr/w hstrobe ? hcs hd[31:0] (output) hrdy 8 9 7 2 1 2 1 15 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 7?36. hpi32 read timing (has not used, tied high) 8 6 15 9 7 3 18 11 10 11 10 19 has ? hcntl[1:0] hr/w hstrobe ? hcs hd[31:0] (output) hrdy ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 7?37. hpi32 read timing (has used) host-port interface (hpi) timing 129 april 2004 ? revised january 2006 sprs247f 13 12 14 3 2 1 2 1 has hcntl[1:0] hr/w hstrobe ? hcs hd[31:0] (input) hrdy 6 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 7?38. hpi32 write timing (has not used, tied high) 13 12 14 3 18 11 10 11 10 19 has ? hcntl[1:0] hr/w hstrobe ? hcs hd[31:0] (input) hrdy 6 ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 7?39. hpi32 write timing (has used) multichannel buffered serial port (mcbsp) timing 130 april 2004 ? revised january 2006 sprs247f 7.12 multichannel buffered serial port (mcbsp) timing table 7?26. timing requirements for mcbsp ?? (see figure 7?40) no. ?400 ?500 unit no. min max unit 2 t c(ckrx) cycle time, clkr/x clkr/x ext 4p or 6.67 ? ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext 0.5t c(ckrx) ? 1 ? ns 5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr int 9 ns 5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr ext 1.3 ns 6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr int 6 ns 6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr ext 3 ns 7 t su(drv-ckrl) setup time, dr valid before clkr low clkr int 8 ns 7 t su(drv-ckrl) setup time, dr valid before clkr low clkr ext 0.9 ns 8 t h(ckrl-drv) hold time, dr valid after clkr low clkr int 3 ns 8 t h(ckrl-drv) hold time, dr valid after clkr low clkr ext 3.1 ns 10 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx int 9 ns 10 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx ext 1.3 ns 11 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx int 6 ns 11 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx ext 3 ns ? clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. use whichever value is greater. minimum clkr/x cycle times must be met, even when clkr/x is generated by an internal clock source. the minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timi ng requirements. ? this parameter applies to the maximum mcbsp frequency. operate serial clocks (clkr/x) in the reasonable range of 40/60 duty cyc le. multichannel buffered serial port (mcbsp) timing 131 april 2004 ? revised january 2006 sprs247f table 7?27. switching characteristics over recommended operating conditions for mcbsp ?? (see figure 7?40) no. parameter ?400 ?500 unit no. parameter min max unit 1 t d(cksh-ckrxh) delay time, clks high to clkr/x high for internal clkr/x generated from clks input 1.4 10 ns 2 t c(ckrx) cycle time, clkr/x clkr/x int 4p or 6.67 ?# ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int c ? 1 || c + 1 || ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int ?2.1 3 ns 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx int ?1.7 3 ns 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext 1.7 9 ns 12 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit clkx int ?3.9 4 ns 12 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high clkx ext 2 9 ns 13 t d(ckxh-dxv) delay time, clkx high to dx valid clkx int ?3.9 + d1 4 + d2 ns 13 t d(ckxh-dxv) delay time, clkx high to dx valid clkx ext 2.0 + d1 9 + d2 ns 14 t d(fxh-dxv) delay time, fsx high to dx valid fsx int ?2.3 + d1 5.6 + d2 ns 14 t d(fxh-dxv) only applies when in data delay 0 (xdatdly = 00b) mode fsx ext 1.9 + d1 9 + d2 ns ? clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. ? minimum delay times also represent minimum output hold times. minimum clkr/x cycle times must be met, even when clkr/x is generated by an internal clock source. minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timing requirements. ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. # use whichever value is greater. || c = h or l s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the maximum limit (see ? footnote above). extra delay from clkx high to dx valid applies only to the first data bit of a device , if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 4p, d2 = 8p extra delay from fsx high to dx valid applies only to the first data bit of a device , if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 4p, d2 = 8p multichannel buffered serial port (mcbsp) timing 132 april 2004 ? revised january 2006 sprs247f bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xdatdly=00b) dx ? parameter no. 13 applies to the first data bit only when xdatdly 0 13 ? 13 ? figure 7?40. mcbsp timing table 7?28. timing requirements for fsr when gsync = 1 (see figure 7?41) no. ?400 ?500 unit no. min max unit 1 t su(frh-cksh) setup time, fsr high before clks high 4 ns 2 t h(cksh-frh) hold time, fsr high after clks high 4 ns 2 1 clks fsr external clkr/x (no need to resync) clkr/x (needs resync) figure 7?41. fsr timing when gsync = 1 multichannel buffered serial port (mcbsp) timing 133 april 2004 ? revised january 2006 sprs247f table 7?29. timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 7?42) no. ?400 ?500 unit no. master slave unit min max min max 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 ? 12p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 24p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. table 7?30. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 7?42) no. parameter ?400 ?500 unit no. parameter master slave unit min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? t ? 2 t + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # l ? 2 l + 3 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ?2 4 12p + 2.8 20p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low l ? 2 l + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 4p + 3 12p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 8p + 1.8 16p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 7?42. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 multichannel buffered serial port (mcbsp) timing 134 april 2004 ? revised january 2006 sprs247f table 7?31. timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 7?43) no. ?400 ?500 unit no. master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 12p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 24p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. table 7?32. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 7?43) no. parameter ?400 ?500 unit no. parameter master slave unit min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? l ? 2 l + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # t ? 2 t + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ?2 4 12p + 2.8 20p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low ?2 4 12p + 3 20p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid h ? 2 h + 4 8p + 2 16p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5 figure 7?43. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 multichannel buffered serial port (mcbsp) timing 135 april 2004 ? revised january 2006 sprs247f table 7?33. timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 7?44) no. ?400 ?500 unit no. master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 12p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 24p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. table 7?34. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 7?44) no. parameter ?400 ?500 unit no. parameter master slave unit min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? t ? 2 t + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # h ? 2 h + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ?2 4 12p + 2.8 20p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high h ? 2 h + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 4p + 3 12p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 8p + 2 16p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 7?44. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 multichannel buffered serial port (mcbsp) timing 136 april 2004 ? revised january 2006 sprs247f table 7?35. timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 7?45) no. ?400 ?500 unit no. master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 12p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 24p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. table 7?36. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 7?45) no. parameter ?400 ?500 unit no. parameter master slave unit min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? h ? 2 h + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # t ? 2 t + 1 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ?2 4 12p + 2.8 20p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high ?2 4 12p + 3 20p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid l ? 2 l + 4 8p + 2 16p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr figure 7?45. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 timer timing 137 april 2004 ? revised january 2006 sprs247f 7.13 timer timing table 7?37. timing requirements for timer inputs ? (see figure 7?46) no. ?400 ?500 unit no. min max unit 1 t w(tinph) pulse duration, tinp high 8p ns 2 t w(tinpl) pulse duration, tinp low 8p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. table 7?38. switching characteristics over recommended operating conditions for timer outputs ? (see figure 7?46) no. parameter ?400 ?500 unit no. parameter min max unit 3 t w(touth) pulse duration, tout high 8p ?3 ns 4 t w(toutl) pulse duration, tout low 8p ?3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. tinpx toutx 4 3 2 1 figure 7?46. timer timing general-purpose input/output (gpio) port timing 138 april 2004 ? revised january 2006 sprs247f 7.14 general-purpose input/output (gpio) port timing table 7?39. timing requirements for gpio inputs ?? (see figure 7?47) no. ?400 ?500 unit no. min max unit 1 t w(gpih) pulse duration, gpix high 8p ns 2 t w(gpil) pulse duration, gpix low 8p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. ? the pulse width given is suf ficient to generate a cpu interrupt or an edma event. however, if a user wants to have the dsp reco gnize the gpix changes through software polling of the gpio register, the gpix duration must be extended to at least 12p to allow the dsp enough time to access the gpio register through the cfgbus. table 7?40. switching characteristics over recommended operating conditions for gpio outputs ? (see figure 7?47) no. parameter ?400 ?500 unit no. parameter min max unit 3 t w(gpoh) pulse duration, gpox high 24p ? 8 ns 4 t w(gpol) pulse duration, gpox low 24p ? 8 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 500 mhz, use p = 2 ns. this parameter value should not be used as a maximum performance specification. actual performance of back-to-back accesses of the gpio is dependent upon internal bus activity. gpix gpox 4 3 2 1 figure 7?47. gpio port timing jtag test-port timing 139 april 2004 ? revised january 2006 sprs247f 7.15 jtag test-port timing table 7?41. timing requirements for jtag test port (see figure 7?48) no. ?400 ?500 unit no. min max unit 1 t c(tck) cycle time, tck 35 ns 3 t su(tdiv-tckh) setup time, tdi/tms/trst valid before tck high 10 ns 4 t h(tckh-tdiv) hold time, tdi/tms/trst valid after tck high 9 ns table 7?42. switching characteristics over recommended operating conditions for jtag test port (see figure 7?48) no. parameter ?400 ?500 unit no. parameter min max unit 2 t d(tckl-tdov) delay time, tck low to tdo valid 0 18 ns tck tdo tdi/tms/trst 1 2 3 4 2 figure 7?48. jtag test-port timing mechanical data 140 april 2004 ? revised january 2006 sprs247f 8 mechanical data 8.1 thermal data the following tables show the thermal resistance characteristics for the pbga ? gts and zts mechanical packages. table 8?1. thermal resistance characteristics (s-pbga package) [gts] no. c/w board type ? air flow (m/s ? ) 1 r jc junction-to-case 5.60 jedec low-k test card n/a 2 r jb junction-to-board 9.37 jedec high-k test card n/a 3 20.8 jedec high-k test card 0.00 4 r ja junction-to-free air 16.8 jedec high-k test card 0.5 5 r ja junction-to-free air 15.4 jedec high-k test card 1.0 6 14.1 jedec high-k test card 2.00 1.87 jedec high-k test card 0.00 7 psi jt junction-to-package top 1.98 jedec high-k test card 0.5 7 psi jt junction-to-package top 2.03 jedec high-k test card 1.0 2.12 jedec high-k test card 2.00 11.1 jedec high-k test card 0.00 8 psi jb junction-to-board 10.4 jedec high-k test card 0.5 8 psi jb junction-to-board 10.3 jedec high-k test card 1.0 10.1 jedec high-k test card 2.00 ? board types are as defined by jedec. reference jedec standard jesd51?9. test boards for area array surface mount package therma l measurements. ? m/s = meters per second table 8?2. thermal resistance characteristics (s-pbga package) [zts] no. c/w board type ? air flow (m/s ? ) 1 r jc junction-to-case 5.60 jedec low-k test card n/a 2 r jb junction-to-board 9.37 jedec high-k test card n/a 3 20.8 jedec high-k test card 0.00 4 r ja junction-to-free air 16.8 jedec high-k test card 0.5 5 r ja junction-to-free air 15.4 jedec high-k test card 1.0 6 14.1 jedec high-k test card 2.00 1.87 jedec high-k test card 0.00 7 psi jt junction-to-package top 1.98 jedec high-k test card 0.5 7 psi jt junction-to-package top 2.03 jedec high-k test card 1.0 2.12 jedec high-k test card 2.00 11.1 jedec high-k test card 0.00 8 psi jb junction-to-board 10.4 jedec high-k test card 0.5 8 psi jb junction-to-board 10.3 jedec high-k test card 1.0 10.1 jedec high-k test card 2.00 ? board types are as defined by jedec. reference jedec standard jesd51?9. test boards for area array surface mount package therma l measurements. ? m/s = meters per second mechanical data 141 april 2004 ? revised january 2006 sprs247f 8.2 packaging information the following packaging information reflects the most current released data available for the designated device(s). this data is subject to change without notice and without revision of this document. package option addendum www.ti.com 2-apr-2012 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) tms320c6410gts400 active fcbga gts 288 60 tbd snpb level-4-220c-72 hr tms320c6410zts400 active fcbga zts 288 60 pb-free (rohs exempt) snagcu level-4-260c-72hr tms320c6410ztsa400 active fcbga zts 288 60 pb-free (rohs exempt) snagcu level-4-260c-72hr tms320c6413gts500 active fcbga gts 288 60 tbd snpb level-4-220c-72 hr tms320c6413gtsa500 active fcbga gts 288 60 tbd snpb level-4-220c-72 hr TMS320C6413ZTS500 active fcbga zts 288 60 pb-free (rohs exempt) snagcu level-4-260c-72hr tms320c6413ztsa500 active fcbga zts 288 60 pb-free (rohs exempt) snagcu level-4-260c-72hr tmx320c6410gts obsolete fcbga gts 288 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. package option addendum www.ti.com 2-apr-2012 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or " enhanced plastic. " only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer ' s risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap mobile processors www.ti.com/omap wireless connectivity www.ti.com/wirelessconnectivity ti e2e community home page e2e.ti.com mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2012, texas instruments incorporated |
Price & Availability of TMS320C6413ZTS500
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |